PCIM: A Physically Based Continuous Short-Channel IGFET Model for Circuit Simulation

IEEE Transactions on Electron Devices

Volumn 41, Issue 6, 1994, Pages 988-997

  Arora, Narain D ^a   Rios, Rafael ^a   Huang, Cheng Liang ^a   Raol, Kartik ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CHARGE CARRIERS; CMOS INTEGRATED CIRCUITS; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER SIMULATION; CONVERGENCE OF NUMERICAL METHODS; ELECTRIC CURRENTS; ELECTRIC RESISTANCE; GATES (TRANSISTOR); MATHEMATICAL MODELS; PARAMETER ESTIMATION; THERMAL EFFECTS;

CARRIER MOBILITY; CHANNEL LENGTH MODULATION; DRAIN CONDUCTANCE EQUATION; DRAIN CURRENT EQUATION; INTRINSIC GATE CAPACITANCE; PCIM CIRCUIT MODEL; SOFTWARE PACKAGE SPICE; SUB HALF MICRON CHANNEL LENGTHS; THRESHOLD VOLTAGE; VELOCITY SATURATION;

MOSFET DEVICES;

EID: 0028446654     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.293312     Document Type: Article

References (36)

1. H. J. Park, P. K. Ko, and C. Hu, “A charge sheet capacitance model of short channel MOSFET’s for SPICE,” IEEE Trans. Computer-Aided Design, vol. 10, pp. 376-389, 1991.
2. A. R. Boothroyd, S. W. Tarasewicz, and C. Slaby, “MISNAN—a physically based continuous MOSFET model for CAD applications,” IEEE Trans. Compter-Aided Design, vol. 10, pp. 1512-1529, 1991.
3. J. A. Power and W. A. Lane, “Enhanced SPICE MOSFET model for analog applications including parameter extraction schemes,” Proc. IEEE 1990 Int. Conf. Microelectronics Test Structures, 1990, vol. 3, pp. 129-134.
4. C. C. McAndrew, B. K. Bhattacharyya, and O. Wing, “A single-piece Coo-continuous MOSFET model including subthreshold conduction,” IEEE Electron Device Lett., vol. 12, pp. 565-567, 1991.
5. S. Veeraraghavan, “SSIM: a new charge-based MOSFET model,” presented at the MCNC Circuit Simulation Workshop, Nov. 1990.
6. A. Vladimirescu and S. Liu, “The simulation of MOS integrated circuits using SPICE2,” Univ. Calif., Berkeley, Memo UCB-ERL M80/7, 1980.
7. P. Yang and P. K. Chatterjee, “SPICE modeling for small geometry MOSFET circuits,” IEEE Trans. Comp.-Aided Design, vol. CAD-1, pp. 169-182, 1982.
8. H. I. Hanafi, L. H. Camnitz, and A. J. Dally, “An accurate and simple MOSFET model for compter-aided design, ' ‘'IEEE J. Solid-State Circuits, vol. SC-17, pp. 882-89, 1982.
9. B. J. Sheu, D. L. Scharfetter, P. K. Ko, and M. C. Jeng, “BSIM: Berkeley short-channel IGFET model for MOS transistors,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 558-565, 1987.
10. Y. P. Tsividis, Operation and Modeling of The MOS Transistor. New York-. McGraw-Hill, 1987.
11. N. D. Arora and L. M. Richardson, “MOSFET modeling for circuit simulation,” in Advanced MOS Device Physics, VLSI Electronics: Microstructure Science, N. G. Einspruch and G. Gildenblat, Eds. New York: Academic, 1989, vol. 18, 236-276.
12. H. C. de Graaff and F. M. Klaassen, Compact Transistor Modelling for Circuit Design. Vienna/New York: Springer-Verlag, 1990.
13. N. D. Arora, MOSFET Models for VLSI Circuit Simulation—Theory and Practice. New York/Vienna: Springer-Verlag, 1993.
14. N. D. Arora and M. Sharma, “MOSFET substrate current model for circuit simulation,” IEEE Trans. Electron Devices, vol. 38, pp. 1392-1398, 1991.
15. R. Coen and R. S. Muller, “Velocity of surface carriers in inversion layers of silicon,” Solid-State Electron., vol. 23, pp. 35-40, 1980.
16. T. Y. Chan, S. W. Lee, and H. Gaw, “Experimental characterization and modeling of electron saturation velocity in MOSFET’s inversion layer from 90 to 350 K,” IEEE Electron Devices Lett., vol. 2, pp. 466-468, 1990.
17. G. W. Taylor, “Velocity-saturated characteristics of short-channel MOSFETs,” AT&T Bell Syst. Techn. J., vol. 63, pp. 1325-1381, 1984.
18. T. Grotjohn and B. Hoefflinger, “A parametric short-channel MOS transistor model for subthreshold and strong inversion current,” IEEE Trans. Electron Devices, ED-31, pp. 109-112, 1984.
19. G. T. Wright, “Simple and continuous MOSFET models for the computer-aided-design of VLSI,” Proc. Inst. Elec. Eng., vol. 132, pt. I, pp. 187-194, 1985.
20. N. D. Arora, “Semi-empirical model for the threshold voltage of a double implanted MOSFET and its temperature dependence,” Solid-State Electron. 30, pp. 559-569, 1987.
21. N. D. Arora and M. Sharma “Modeling the anomalous threshold voltage behavior of submicron MOSFETs,” IEEE Electron Devices Lett., vol. 13, pp. 92-94, 1992.
22. M. J. Deen and Z. X. Yan, “Substrate bias effects on drain-induced barrier lowering in short-channel PMOS devices,” IEEE Trans. Electron Devices, vol. 37, pp. 1707-1713, 1990.
23. G. Merckel, J. Borel, and N. Z. Cupcea, “An accurate large-signal MOS transistror model for computer-aided-design,” IEEE Trans. Electron Devices, vol. ED-19, pp. 681-690, 1972.
24. M. Shur, T. A. Fjeldly, T. Ytterdal, and K. Lee, “A unified MOSFET Model,” Solid-State Electron., 35, pp. 1795-1802, 1992.
25. N. D. Arora and G. Sh. Gildenblat, “A semi-empirical model of the MOSFET inversion layer mobility for low-temperature operation,” IEEE Trans. Electron Devices, vol. ED-34, pp. 89-93, 1987.
26. S. W. Lee, “Universality of mobility-gate field characteristics of electrons in the inversion charge layer and its application in MOSFET modeling,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 724-730, 1989.
27. C.-L. Huang and N. D. Arora, “Characterization and modeling of the n- and p-channel MOSFETs inversion-layer mobility in the temperature range 25 to 125°C,” Solid-State Electron., vol. 37, pp. 97-104, 1994.
28. P. K. Ko “Approaches to scaling" in Advanced MOS Device Physics, N. G. Einspruch and G. Gildenblat, Eds. VLSI Electronics: Microstructure Science. New York: Academic, 1989, vol. 18, pp. 1-37.
29. D. Ward and R. W. Dutton, “A charge-oriented model for MOS transistor capacitances,” IEEE J. Solid-State Circuits, vol. SC-13, pp. 703-707, 1978. Also see D. Ward, “Charge-based modeling of capacitances in MOS transistors,” Stanford University Tech. Rep. G201-11, 1982.
30. T. Smedes and F. M. Klaassen, “Effects of the lightly doped drain configuration on capacitance characteristics of submicron MOSFETs" in IEDM Tech. Dig., pp. 197-200, 1990.
31. M. Sharma and N. D. Arora, “OPTIMA: A nonlinear model parameter extraction program with statistical confidence region algorithms,” IEEE Trans. Comp.-Aided Design, vol. 12, pp. 982-986, 1993.
32. K. Doganis and D. L. Scharfetter, “General optimization and extraction of IC device model parameters,” IEEE Trans. Electron Devices vol. ED-30, 1219-1228, 1983.
33. P. Yang and P. K. Chatterjee, “An optimal parameter extraction program for MOSFET models,” IEEE Trans. Electron Devices, vol. ED-30, pp. 1214-1219, 1983.
34. W. Maes, K. M. De Meyer, and L. H. Dupas, “SIMPAR: A versatile technology independent parameter extraction program using new optimized fit strategy,” IEEE Trans. Comp.-Aided Design, vol. CAD-5, pp. 320-325, 1986.
35. P. Klein, K. Hoffmann, and B. Lemaitre, “Description of the bias dependent overlap capacitance at LDD MOSFETs for circuit applications,” in IEDM Tech. Dig., pp. 493-496, 1993.
36. Y. Tsividis and K. Suyama, “MOSFET modeling for analog circuit CAD: Problems and prospects,” Tech. Dig. vol. CICC-93, pp. 14.1.1-14.1.6, 1993.