Behavior of copper contamination on backside damage for ultra-thin silicon three dimensional stacking structure

Microelectronic Engineering

Volumn 167, Issue , 2017, Pages 23-31

  Mizushima, Yoriko ^a,b   Kim, Youngsuk ^a,c   Nakamura, Tomoji ^b   Uedono, Akira ^d   Ohba, Takayuki ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^b FUJITSU LABORATORIES LTD   (Japan)

^c DISCO CORPORATION   (Japan)

^d UNIVERSITY OF TSUKUBA   (Japan)

Author keywords

3D integration; Cu contamination; Grinding damage; Positron annihilation; Ultra thinning; Wafer on wafer

Indexed keywords

CONTAMINATION; COPPER; GRINDING (MACHINING); HIGH RESOLUTION TRANSMISSION ELECTRON MICROSCOPY; MASS SPECTROMETRY; POSITRON ANNIHILATION; POSITRON ANNIHILATION SPECTROSCOPY; POSITRONS; SECONDARY ION MASS SPECTROMETRY; SILICON WAFERS; TRANSMISSION ELECTRON MICROSCOPY;

3-D INTEGRATION; DEVICE CHARACTERISTICS; GRINDING DAMAGE; ON-WAFER; SECONDARY ION MASS SPECTROSCOPY; THREE DIMENSIONAL STACKING; ULTRA-THINNING; VACANCY-TYPE DEFECTS;

WAFER BONDING;

EID: 84992630724     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2016.10.010     Document Type: Article

References (21)

1. [1] Bower, C.A., Malta, D., Temple, D., Robinson, J.E., Coffman, P.R., Skokan, M.R., Welch, T.B., High density vertical interconnects for 3-D integration of silicon integrated circuits. Proc. ECTC, 2006, 399.
2. [2] Burns, J.A., Aull, B.F., Chen, C.K., Chen, C.L., Keast, C.L., Knecht, J.M., Suntharalingam, V., Warner, K., Wyatt, P.W., Yost, D.R.W., A wafer-scale 3-D circuit integration technology. IEEE Trans. Electron Devices, 53, 2006, 2507.
3. [3] Ohba, T., Maeda, N., Kitada, H., Fujimoto, K., Suzuki, K., Nakamura, T., Kawai, A., Arai, K., Thinned wafer multi-stack 3DI technology. Microelectron. Eng., 87, 2010, 485.
4. [4] Ohba, T., Bumpless Through-Dielectrics-Silicon-Via (TDSV) technology for wafer-based three-dimensional integration (3DI). ECS Trans., 44(1), 2012, 827.
5. [5] Kim, Y.S., Maeda, N., Kitada, H., Fujimoto, K., Kodam, S., Kawai, A., Arai, K., Suzuki, K., Nakamura, T., Ohba, T., Advanced wafer thinning technology and feasibility test for 3D integration. Microelectron. Eng. 107 (2013), 65–71, 10.1016/j.mee.2012.10.025.
6. [6] Kim, Y.S., Tsukune, A., Maeda, N., Kitada, H., Kawai, A., Arai, K., Fujimoto, K., Suzuki, K., Mizushima, Y., Nakamura, T., Ohba, T., Futatsugi, T., Miyajima, M., Ultra thinning 300-mm wafer down to 7-μm for 3D wafer integration on 45-nm node CMOS using strained silicon and Cu/low-k interconnects. IEDM Tech. Dig., 2009, 365.
7. [7] Maeda, N., Kim, Y.S., Hikosaka, Y., Eshita, T., Kitada, H., Fujimoto, K., Mizushima, Y., Suzuki, K., Nakamura, T., Kawai, A., Arai, K., Ohba, T., Development of sub 10-μm ultra-thinning technology using device wafers for 3D manufacturing of terabit memory. Proc. VLSI Technol., 2010, 105.
8. [8] Kim, Y.S., Kodama, S., Mizushima, Y., Maeda, N., Kitada, H., Fujimoto, K., Nakamura, T., Suzuki, D., Kawai, A., Arai, K., Ohba, T., Ultra Thinning down to 4-mm using 300-mm wafer proven by 40-nm node 2 Gb DRAM for 3D multi-stack WOW applications. Symp. VLSI Tech. Dig., 2014, 1–2, 10.1109/VLSIT.2014.6894347.
9. [9] Istoratov, A.A., Weber, E.R., Physics of copper in silicon. J. Electrochem. Soc., 149(1), 2002, G21.
10. [10] Hozawa, K., Miyazaki, H., Yugami, J., True influence of wafer-backside copper contamination during the back-end process on device characteristics. IEDM Tech. Dig., 2002, 737.
11. [11] Hozawa, K., Takeda, K., Torii, K., Impact of backside Cu contamination in the 3D integration process. VLSI Technol. Dig. Tech. Pap., 2009, 173.
12. [12] Lee, K.W., Bea, J.C., Ohara, Y., Murugesan, M., Fukushima, T., Tanaka, T., Koyanagi, M., “Impacts of Cu contamination on device reliabilities in 3-D IC integration”. IEEE Trans. Device Mater. Reliab., 14(1), 2014, 10.1109/TDMR.2013.2258022.
13. [13] Kim, Y.S., Kodama, S., Mizushima, Y., Nakamura, T., Maeda, N., Fujimoto, K., Kawai, A., Arai, K., Ohba, T., A robust wafer thinning down to 2.6-μm for bumpless interconnects and DRAM WOW application. IEDM Tech. Dig., 2015, 189.
14. [14] Wang, P., Chang, L., Demer, L.J., Varker, C.J., Denuded zones in Czochralski silicon wafers. J. Electrochem. Soc., 131(8), 1984, 10.1149/1.2115998.
15. [15] 300 mm Si wafers product data of Shin-Etsu Chemical Co., Ltd. https://www.shinetsu.co.jp/en/products/pdf/c401.pdf.
16. [16] Morinaga, H., Suyama, M., Nose, M., Verhaverbeke, S., Ohmi, T., A model for the electrochemical deposition and removal of metallic impurities on Si surfaces. IEICE Trans. Electron., E79-C, 1996, 343.
17. [17] Mizushima, Y., Kim, Y.S., Nakamura, T., Sugie, R., Hashimoto, H., Uedono, A., Ohba, T., Impact of back-grinding-induced damage on Si wafer thinning for three-dimensional integration. Jpn. J. Appl. Phys., 53, 2014, 10.7567/JJAP.53.05GE04 05GE04.
18. [18] Leipner, H.S., Mikhnovich, V.V. Jr., Bondarenko, V., Wang, Z., Gu, H., Krause-Rehberg, R., Demenet, J.-L., Rabier, J., Positron annihilation of defects in silicon deformed at different temperatures. Physica B 340–342 (2003), 617–621.
19. [19] Uedono, A., Tsutsui, K., Ishibashi, S., Watanabe, H., Kubota, S., Nakagawa, Y., Mizuno, B., Hattori, T., Iwai, H., Vacancy-boron complexes in plasma immersion ion-implanted Si probed by a monoenergetic positron beam. Jpn. J. Apply. Phys., 49, 2010, 051301.
20. [20] Uedono, A., Mizushima, Y., Kim, Y., Nakamura, T., Ohba, T., Yoshihara, N., Oshima, N., Suzuki, R., Vacancy-type defects induced by grinding of Si wafers studied by monoenergetic positron beams. J. Appl. Phys., 116, 2014, 134501, 10.1063/1.4896829.
21. [21] Weber, E.R., Transition metals in silicon. Appl. Phys. A30 (1983), 1–22.