Development of sub 10-μm ultra-thinning technology using device wafers for 3D manufacturing of terabit memory

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2010, Pages 105-106

  Maeda, N ^a   Kim, Y S ^b   Hikosaka, Y ^b   Eshita, T ^b   Kitada, H ^a   Fujimoto, K ^c   Mizushima, Y ^b   Suzuki, K ^c   Nakamura, T ^b   Kawai, A ^d   Arai, K ^d   Ohba, T ^a  

^a UNIVERSITY OF TOKYO   (Japan)

^b FUJITSU LABORATORIES LTD   (Japan)

^c DAI NIPPON PRINTING CO LTD   (Japan)

^d DISCO CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL MECHANICAL PLANARIZATIONS; CMOS LOGIC; CRYSTALLINE LAYERS; DEVICE WAFERS; HIGH RATE; JUNCTION LEAKAGE CURRENTS; SWITCHING CHARGE; TERABIT; THINNING PROCESS; THROUGH-SILICON-VIA;

ASPECT RATIO; FERROELECTRIC DEVICES; LOGIC DEVICES;

SILICON WAFERS;

EID: 77957882524     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2010.5556188     Document Type: Conference Paper

References (5)

1. T. Ohba, et al., Microelectronic Eng., 87 (2010) 485.
2. N. Maeda, et al, Proc. AMC (2008) 91.
3. H. Kitada, et al., Proc. IITC (2009) 107.
4. K. Hozawa, et al., Proc. VLSI (2009) 172.
5. Y. S. Kim, et al., Proc. IEDM (2009) 365.