True influence of wafer-backside copper contamination during the back-end process on device characteristics

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2002, Pages 737-740

  Hozawa, Kazuyuki ^a   Miyazaki, Hiroshi ^b   Yugami, Jiro ^b  

^a HITACHI LTD   (Japan)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CMOS INTEGRATED CIRCUITS; FLUORESCENCE; INTERFACES (MATERIALS); MOS CAPACITORS; SILICA; SILICON WAFERS; X RAY ANALYSIS;

SINGLE-WAFER PROCESS;

MOSFET DEVICES;

EID: 0036931229     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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7. K. Takeda, K. Hinode, I. Oodake, N. Oohashi, and H. Yamaguchi, "Enhanced Dielectric Breakdown Lifetime of the Copper/Silicon Nitride/Silicon Dioxide Structure," IEEE Proc. IRPS 1998, p. 36 (1998).
8. K. Hozawa, T. Itoga, S. Isomae, and M. Ohkura, "Re-distribution of Cu contamination in advanced high-speed CMOS and its influence on device characteristics," IEEE Symp. VLSI Technology Tech. Dig. p. 129 (1999).