Advanced wafer thinning technology and feasibility test for 3D integration

Microelectronic Engineering

Volumn 107, Issue , 2013, Pages 65-71

  Kim, Young Suk ^a,b   Maeda, Nobuhide ^a   Kitada, Hideki ^a   Fujimoto, Koji ^a   Kodama, Shoichi ^a   Kawai, Akihito ^b   Arai, Kazuhisa ^b   Suzuki, Kousuke ^c   Nakamura, Tomoji ^d   Ohba, Takayuki ^a  

^a UNIVERSITY OF TOKYO   (Japan)

^b DISCO CORPORATION   (Japan)

^c DAI NIPPON PRINTING CO LTD   (Japan)

^d FUJITSU LABORATORIES LTD   (Japan)

Author keywords

Auto TTV; Back grind (BG); CMOS; FRAM; Gettering; Leakage current; Mobility; Strain transistor; Three dimensional (3D) integration; Through Silicon Via; Total thickness variation; TSV; Wafer on wafer (WOW)

Indexed keywords

CARRIER MOBILITY; CMOS INTEGRATED CIRCUITS; DEBONDING; ELECTRONICS PACKAGING; FERROELECTRIC DEVICES; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATION; LEAKAGE CURRENTS; SILICON WAFERS; SURFACE DEFECTS; SURFACE TREATMENT; THRESHOLD VOLTAGE; WAFER BONDING;

AUTO-TTV; BACK GRIND (BG); FRAM; GETTERING; ON-WAFER; THREE DIMENSIONAL (3D) INTEGRATION; THROUGH-SILICON-VIA; TOTAL THICKNESS VARIATIONS;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 84886900382     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2012.10.025     Document Type: Article

References (12)

1. J.F. Gibbons, K.F. Lee, IEEE Trans. Electron Devices Lett. 1 (6) (1980) 117-118.
2. S. Kawamura, N. Sasaki, T. Iwai, M. Nakano, M. Takagi, IEEE Trans. Electron Devices Lett. 4 (10) (1983) 366-368.
3. M. Koyanagi, H. Kurino, K.W. Lee, K. Sakuma, N. Miyakawa, H. Itani, IEEE Micro. 18 (4) (1998) 17-22.
4. K.W. Lee, T. Nakamura, T. Ono, Y. Yamada, T. Mizukusa, H. Hashimoto, K.T. Park, H. Kurino, M. Koyanagi, IEEE IEDM Tech. Dig. (2000) 165-168.
5. T. Ohba, N. Maeda, H. Kitada, K. Fujimoto, K. Suzuki, T. Nakamura, A. Kawai, K. Arai, Microelectron. Eng. 87 (3) (2010) 485-490.
6. Y.S. Kim, A. Tsukune, N. Maeda, H. Kitada, A. Kawai, K. Arai, K. Fujimoto, K. Suzuki, Y. Mizushima, T. Nakamura, T. Ohba, T. Futatsugi, M. Miyajima, IEEE IEDM Tech. Dig. (2007) 365-368.
7. N. Maeda, Y.S. Kim, Y. Hikosaka, T. Eshita, H. Kitada, K. Fujimoto, Y. Mizushima, K. Suzuki, T. Nakamura, A. Kawai, K. Arai, T. Ohba, IEEE Symp. VLSI Technol. (2010) 105-106.
8. S.E. Thompson, M. Armstrong, C. Auth, M. Alvi, M. Buehler, R. Chau, S. Cea, T. Ghani, IEEE Trans. Electron Devices 51 (11) (2004) 1790-1797.
9. K. De Munck, T. Chiarella, P. De Moor, B. Swinnen, C. Van Hoof, IEEE Trans. Electron Devices Lett. 29 (4) (2008) 322-324.
10. T. Yamazaki, K. Inoue, H. Miyazawa, M. Nakamura, N. Sashida, R. Satomi, A. Kerry, Y. Katoh, H. Noshiro, K. Takai, R. Shinohara, C. Ohno, T. Nakajima, Y. Furumura, S. Kawamura, IEEE IEDM Tech. Dig. (1997) 613-616.
11. Y. Horii, Y. Hikosaka, A. Itoh, K. Matsuura, M. Kurasawa, G. Komuro, K. Maruyama, T. Eshita, S. Kashiwagi, IEEE IEDM Tech. Dig. (2002) 539-542.
12. Y. Nagano, T. Mikawa, T. Kutsunai, S. Hayashi, T. Nasu, S. Natsume, T. Tatsunari, T. Ito, S. Goto, H. Yano, A. Noma, K. Nagahashi, T. Miki, M. Sakagami, Y. Izutsu, T. Nakakuma, H. Hirano, S. Iwanari, Y. Murakuki, K. Yamaoka, Y. Goho, Y. Judai, E. Fujii, K. Sato, IEEE Symp. VLSI Technol. (2003) 171-172.