A robust wafer thinning down to 2.6-μm for bumpless interconnects and DRAM WOW applications

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2016-February, Issue , 2015, Pages 8.3.1-8.3.4

  Kim, Y S ^a,b   Kodama, S ^a,b   Mizushima, Y ^a,c   Nakamura, T ^a,c   Maeda, N ^a,b   Fujimoto, K ^a,d   Kawai, A ^b   Arai, K ^b   Ohba, T ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^b DISCO CORPORATION   (Japan)

^c FUJITSU LABORATORIES LTD   (Japan)

^d DAI NIPPON PRINTING CO LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; ELECTRON DEVICES;

PACKAGE LEVELS; RETENTION CHARACTERISTICS; THICKNESS UNIFORMITY; WAFER THINNING;

SILICON WAFERS;

EID: 84964049809     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2015.7409653     Document Type: Conference Paper

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7. Y. S. Kim et al., Symp. VLSI Tech. Dig., 26 (2014)
8. H. Morinaga et al, IEICE Trans. Electron. E79-C, 343 (1996).