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Volumn , Issue , 2016, Pages

Temporal Isolation of Hard Real-Time Applications on Many-Core Processors

Author keywords

[No Author keywords available]

Indexed keywords

EXECUTION MODEL; HARD REAL TIME APPLICATIONS; INTEGRATED AVIONICS SYSTEM; MANY-CORE PROCESSORS; MASSIVELY PARALLELS; REAL TIME; SAFETY CRITICAL APPLICATIONS; TEMPORAL ISOLATION;

EID: 84971328530     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTAS.2016.7461363     Document Type: Conference Paper
Times cited : (24)

References (52)
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    • (2014) CPLEX Optimization Studio
  • 9
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    • Puffitsch, W.1    Noulard, E.2    Pagetti, C.3
  • 13
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    • A calculus for network delay. I. Network elements in isolation
    • R. Cruz, "A calculus for network delay. I. network elements in isolation," IEEE Transactions on Information Theory, vol. 37, no. 1, pp. 114-131, 1991.
    • (1991) IEEE Transactions on Information Theory , vol.37 , Issue.1 , pp. 114-131
    • Cruz, R.1
  • 37
    • 84963692574 scopus 로고    scopus 로고
    • Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources
    • G. Giannopoulou, N. Stoimenov, P. Huang, L. Thiele, and B. D. de Dinechin, "Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources," Real-Time Systems, pp. 1-51, 2015.
    • (2015) Real-Time Systems , pp. 1-51
    • Giannopoulou, G.1    Stoimenov, N.2    Huang, P.3    Thiele, L.4    De Dinechin, B.D.5
  • 38
    • 84938539728 scopus 로고    scopus 로고
    • Towards compositionality in execution time analysis: Definition and challenges
    • S. Hahn, J. Reineke, and R. Wilhelm, "Towards compositionality in execution time analysis: Definition and challenges," SIGBED Review, vol. 12, no. 1, pp. 28-36, 2015.
    • (2015) SIGBED Review , vol.12 , Issue.1 , pp. 28-36
    • Hahn, S.1    Reineke, J.2    Wilhelm, R.3
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    • 27344456043 scopus 로고    scopus 로고
    • Aethereal network on chip: Concepts, architectures, and implementations
    • K. Goossens, J. Dielissen, and A. Radulescu, "Aethereal network on chip: concepts, architectures, and implementations," IEEE Design & Test of Computers, vol. 22, no. 5, pp. 414-421, 2005.
    • (2005) IEEE Design & Test of Computers , vol.22 , Issue.5 , pp. 414-421
    • Goossens, K.1    Dielissen, J.2    Radulescu, A.3
  • 52
    • 84869096276 scopus 로고    scopus 로고
    • Memorycentric Scheduling for Multicore Hard Real-time Systems
    • G. Yao, R. Pellizzoni, S. Bak, E. Betti, and M. Caccamo, "Memorycentric Scheduling for Multicore Hard Real-time Systems," Real-Time Systems, vol. 48, no. 6, pp. 681-715, 2012.
    • (2012) Real-Time Systems , vol.48 , Issue.6 , pp. 681-715
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.