An analyzable memory controller for hard real-time CMPs

IEEE Embedded Systems Letters

Volumn 1, Issue 4, 2009, Pages 86-90

  Paolieri, Marco ^a,b   Quiñones, Eduardo ^a   Cazorla, Francisco J ^a,c   Valero, Mateo ^a,b  

^a BARCELONA SUPERCOMPUTING CENTER   (Spain)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^c CSIC   (Spain)

Author keywords

CMP; DDRx SDRAM; Hard real time; Memory controller; Worst case execution time (WCET)

Indexed keywords

HARD REAL-TIME; HARD REAL-TIME SYSTEMS; HARDWARE RESOURCES; MEMORY ACCESS TIME; MEMORY CONTROLLER; MULTI-CORE PROCESSOR; SDRAM MEMORY; WORST-CASE EXECUTION TIME;

CONTROLLERS; DYNAMIC RANDOM ACCESS STORAGE; ESTIMATION; NANOTECHNOLOGY;

REAL TIME SYSTEMS;

EID: 77955678807     PISSN: 19430663     EISSN: None     Source Type: Journal    
DOI: 10.1109/LES.2010.2041634     Document Type: Article

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