An on-line BIST RAM architecture with self-repair capabilities

IEEE Transactions on Reliability

Volumn 51, Issue 1, 2002, Pages 123-128

  Benso, Alfredo ^b   Chiusano, Silvia ^b   Natale, Giorgio Di ^b   Prinetto, Paolo ^a,b  

^a IEEE   (Italy)

^b POLITECNICO DI TORINO   (Italy)

Author keywords

Built in self repair; Built in self test; On line testing

Indexed keywords

BUILT-IN SELF REPAIR; ONLINE TESTING; REDUNDANCY ALLOCATION; SELF REPAIR COMPUTING;

ALGORITHMS; BUILT-IN SELF TEST; COMBINATORIAL CIRCUITS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SYSTEM RECOVERY; FAILURE ANALYSIS; FAULT TOLERANT COMPUTER SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS; NETWORK PROTOCOLS; STATIC RANDOM ACCESS STORAGE; STORAGE ALLOCATION (COMPUTER);

ONLINE SYSTEMS;

EID: 0036507782     PISSN: 00189529     EISSN: None     Source Type: Journal    
DOI: 10.1109/24.994929     Document Type: Article

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