A simulator for evaluating redundancy analysis algorithms of repairable embedded memories

Records of the IEEE International Workshop on Memory Technology, Design and Testing

Volumn 2002-January, Issue , 2002, Pages 68-73

  Huang, Rei Fu ^a   Li, Jin Fu ^a   Yeh, Jen Chieh ^a   Wu, Cheng Wen ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Algorithm design and analysis; Analytical models; Built in self test; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Electrical fault detection; Fault detection; Redundancy

Indexed keywords

ALGORITHMS; ANALYTICAL MODELS; CIRCUIT SIMULATION; ELECTRIC FAULT LOCATION; ELECTRIC NETWORK ANALYSIS; FAULT DETECTION; MEMORY ARCHITECTURE; REDUNDANCY; REPAIR; SIMULATORS;

ALGORITHM DESIGN AND ANALYSIS; CIRCUIT FAULTS; CIRCUIT TESTING; COMPUTATIONAL MODEL; ELECTRICAL FAULT DETECTIONS;

BUILT-IN SELF TEST;

EID: 0142206047     PISSN: 10874852     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MTDT.2002.1029766     Document Type: Conference Paper

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