A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 2, 1996, Pages 195-201

  Yamagata, Tadato ^a,b,c,d,e   Sato, Hirotoshi ^b,d,f   Fujita, Kore Aki ^b,g   Nishimura, Yasumasa ^b,c,e,h,i   Anami, Kenji ^a,b,e,j,k,l  

^a IEEE

^b MITSUBISHI ELECTRIC CORPORATION   (Japan)

^c OSAKA UNIVERSITY   (Japan)

^d ULSI Laboratory

^e Institute of Electronics   (Japan)

^f OKAYAMA UNIVERSITY   (Japan)

^g KYOTO UNIVERSITY   (Japan)

^h SHIZUOKA UNIVERSITY   (Japan)

ⁱ Mitsubishi's Kita Itami Works   (Japan)

^j KYUSHU UNIVERSITY   (Japan)

^k LSI R and D Laboratory   (Japan)

^l Kita Itami Works ^*

more..

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ESTIMATION; MONTE CARLO METHODS; OPTIMIZATION; RANDOM ACCESS STORAGE; REDUNDANCY; ULSI CIRCUITS;

CHIP AREA PENALTY; DISTRIBUTED GLOBALLY REPLACEABLE REDUNDANCY; YIELD ENHANCEMENT;

SEMICONDUCTOR STORAGE;

EID: 0030082443     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.487996     Document Type: Article

References (11)

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