A Built-in Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 393-402

  Li, Jin Fu ^a   Yeh, Jen Chieh ^b   Huang, Rei Fu ^b   Wu, Cheng Wen ^b   Tsai, Peir Yuan ^c   Hsu, Archer ^c   Chow, Eugene ^c  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^c ADMTek Incorporated   (Taiwan)

Author keywords

Built in redundancy analysis; Built in self repair; Built in self test; Memory testing; Semiconductor memory

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; EMBEDDED SYSTEMS; SEMICONDUCTOR DEVICES;

SEMICONDUCTOR MEMORIES;

STATIC RANDOM ACCESS STORAGE;

EID: 0142246924     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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