Cost-effective clustered architecture

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 1999, Pages 160-168

  Canal, Ramon ^a   Parcerisa, Joan Manuel ^a   Gonzalez, Antonio ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DIGITAL ARITHMETIC; MICROPROCESSOR CHIPS; OPTIMIZATION; RESPONSE TIME (COMPUTER SYSTEMS);

COST-EFFECTIVE CLUSTERED ARCHITECTURES; DYNAMIC STEERING LOGICS; SUPERSCALAR PROCESSORS;

PARALLEL PROCESSING SYSTEMS;

EID: 0033359028     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (20)