Reducing wire delay penalty through value prediction

Proceedings of the Annual International Symposium on Microarchitecture

Volumn , Issue , 2000, Pages 317-326

  Parcerisa, Joan Manuel ^a   Gonzalez, Antonio ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CONSTRAINT THEORY; DATA COMMUNICATION SYSTEMS; HEURISTIC PROGRAMMING; LOGIC PROGRAMMING; OPTIMIZATION; SENSITIVITY ANALYSIS;

INTERCLUSTER COMMUNICATION; WIRE DELAYS;

REDUCED INSTRUCTION SET COMPUTING;

EID: 0034461108     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/360128.360163     Document Type: Conference Paper

References (20)