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Volumn 2144, Issue , 2001, Pages 433-448

A framework for microprocessor correctness statements

Author keywords

[No Author keywords available]

Indexed keywords

FORMAL LOGIC; SPECIFICATIONS;

EID: 84947229460     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44798-9_33     Document Type: Conference Paper
Times cited : (28)

References (33)
  • 1
    • 0026154452 scopus 로고
    • The existence of refinement mappings
    • M. Abadi and L. Lamport. The existence of refinement mappings. Theoretical Computer Science, 2(82):253–284, 1991.
    • (1991) Theoretical Computer Science , vol.2 , Issue.82 , pp. 253-284
    • Abadi, M.1    Lamport, L.2
  • 3
    • 84863896131 scopus 로고    scopus 로고
    • A comparison of two verification methods for speculative instruction execution with exceptions
    • Springer
    • T. Arons and A. Pnueli. A comparison of two verification methods for speculative instruction execution with exceptions. In TACAS, vol 1785 of LNCS, pp 487–502. Springer, 2000.
    • (2000) TACAS , vol.1785 , pp. 487-502
    • Arons, T.1    Pnueli, A.2
  • 4
    • 0345103140 scopus 로고    scopus 로고
    • Using term rewriting systems to design and verify processors
    • Arvind and X. Shen. Using term rewriting systems to design and verify processors. IEEE Micro, 19(3):36–46, 1999.
    • (1999) IEEE Micro , vol.19 , Issue.3 , pp. 36-46
    • Arvindshen, X.1
  • 5
    • 0028579090 scopus 로고
    • Formally verifying a microprocessor using a simulation methodology
    • D. Beatty and R. Bryant. Formally verifying a microprocessor using a simulation methodology. In DAC, pp 596–602, 1994.
    • (1994) DAC , pp. 596-602
    • Beatty, D.1    Bryant, R.2
  • 6
    • 35248886365 scopus 로고    scopus 로고
    • Combining symbolic model checking with uninterpreted functions for out-of-order processor verification
    • LNCS, Springer
    • S. Berezin, A. Biere, E. Clarke, and Y. Zhu. Combining symbolic model checking with uninterpreted functions for out-of-order processor verification. In FMCAD, vol 1522 of LNCS, pp 369–386. Springer, 1998.
    • (1998) FMCAD , vol.1522 , pp. 369-386
    • Berezin, S.1    Biere, A.2    Clarke, E.3    Zhu, Y.4
  • 7
    • 84958772916 scopus 로고
    • Automatic verification of pipelined microprocessor control
    • of LNCS, Springer
    • J. Burch and D. Dill. Automatic verification of pipelined microprocessor control. In CAV, vol 818 of LNCS, pp 68–80. Springer, 1994.
    • (1994) CAV , vol.818 , pp. 68-80
    • Burch, J.1    Dill, D.2
  • 8
    • 0024882158 scopus 로고
    • Verifying pipelined hardware using symbolic logic simulation
    • S. Bose and A. Fisher. Verifying pipelined hardware using symbolic logic simulation. In ICCD, pp 217–221, 1989.
    • (1989) ICCD , pp. 217-221
    • Bose, S.1    Fisher, A.2
  • 9
    • 84957378950 scopus 로고    scopus 로고
    • Processor verification using efficient decision procedures for a logic of uninterpreted functions
    • of LNAI, Springer, June
    • R. Bryant, S. German, and M. Velev. Processor verification using efficient decision procedures for a logic of uninterpreted functions. In TABLEAUX, vol 1617 of LNAI, pp 1–13. Springer, June 1999.
    • (1999) TABLEAUX , vol.1617 , pp. 1-13
    • Bryant, R.1    German, S.2    Velev, M.3
  • 10
    • 0029724075 scopus 로고    scopus 로고
    • Techniques for verifying superscalar microprocessors
    • J. Burch. Techniques for verifying superscalar microprocessors. In DAC, pp 552–557, 1996.
    • (1996) DAC , pp. 552-557
    • Burch, J.1
  • 11
    • 0000938587 scopus 로고    scopus 로고
    • Verifying out-of-order executions
    • Chapman and Hall
    • W. Damm and A. Pnueli. Verifying out-of-order executions. In CHARME, pp 23–47. Chapman and Hall, 1997.
    • (1997) CHARME , pp. 23-47
    • Damm, W.1    Pnueli, A.2
  • 12
    • 0043229196 scopus 로고    scopus 로고
    • An algebraic model of correctness for superscaler microprocessors
    • of LNCS, Springer
    • A. Fox and N. Harman. An algebraic model of correctness for superscaler microprocessors. In Prospects for Hardware Foundations, vol 1546 of LNCS, pp 138–183. Springer, 1998.
    • (1998) Prospects for Hardware Foundations , vol.1546 , pp. 138-183
    • Fox, A.1    Harman, N.2
  • 13
    • 84944407953 scopus 로고    scopus 로고
    • Verifying advanced microarchitectures that support speculation and exceptions
    • of LNCS, Springer
    • R. Hosabettu, G. Gopalakrishnan, and M. Srivas. Verifying advanced microarchitectures that support speculation and exceptions. In CAV, vol 1855 of LNCS, pp 521–537. Springer, 2000.
    • (2000) CAV , vol.1855 , pp. 521-537
    • Hosabettu, R.1    Gopalakrishnan, G.2    Srivas, M.3
  • 14
    • 84863971672 scopus 로고    scopus 로고
    • You assume, we guarantee: Methodology and case studies
    • of LNCS, Springer
    • T. Henzinger, S. Qadeer, and S. Rajamani. You assume, we guarantee: Methodology and case studies. In CAV, vol 1427 of LNCS, pp 440–451. Springer, 1998.
    • (1998) CAV , vol.1427 , pp. 440-451
    • Henzinger, T.1    Qadeer, S.2    Rajamani, S.3
  • 15
    • 33846505764 scopus 로고    scopus 로고
    • Decomposing the proof of correctness of pipelined microprocessors
    • of LNCS, Springer
    • R. Hosabettu, M. Srivas, and G. Gopalakrishnan. Decomposing the proof of correctness of pipelined microprocessors. In CAV, vol 1427 of LNCS, pp 122–134. Springer, 1998.
    • (1998) CAV , vol.1427 , pp. 122-134
    • Hosabettu, R.1    Srivas, M.2    Gopalakrishnan, G.3
  • 16
    • 84957082109 scopus 로고    scopus 로고
    • Proof of correctness of a processor with reorder buffer using the completion functions approach
    • of LNCS, Springer
    • R. Hosabettu, M. Srivas, and G. Gopalakrishnan. Proof of correctness of a processor with reorder buffer using the completion functions approach. In CAV, vol 1633 of LNCS, pp 47–59. Springer, 1999.
    • (1999) CAV , vol.1633 , pp. 47-59
    • Hosabettu, R.1    Srivas, M.2    Gopalakrishnan, G.3
  • 17
    • 84948986759 scopus 로고    scopus 로고
    • Reducing manual abstraction in formal verification of out-of-order execution
    • of LNCS, Springer
    • R. Jones, J. Skakkebæk, and D. Dill. Reducing manual abstraction in formal verification of out-of-order execution. In FMCAD, vol 1522 of LNCS, pp 2–17. Springer, 1998.
    • (1998) FMCAD , vol.1522 , pp. 2-17
    • Jones, R.1    Skakkebæk, J.2    Dill, D.3
  • 18
    • 84947266085 scopus 로고    scopus 로고
    • Correctness of pipelined machines
    • of LNCS, Springer
    • P. Manolios. Correctness of pipelined machines. In FMCAD, vol 1954 of LNCS, pp 161–178. Springer, 2000.
    • (2000) FMCAD , vol.1954 , pp. 161-178
    • Manolios, P.1
  • 19
    • 84863924303 scopus 로고    scopus 로고
    • Verification of an implementation of Tomasulo’s algorithm by compositional model checking
    • of LNCS, Springer
    • K. McMillan. Verification of an implementation of Tomasulo’s algorithm by compositional model checking. In CAV, vol 1427 of LNCS, pp 110–121. Springer, 1998.
    • (1998) CAV , vol.1427 , pp. 110-121
    • McMillan, K.1
  • 20
    • 84988613226 scopus 로고
    • An algebraic definition of simulation between programs
    • The British Comp. Soc
    • R. Milner. An algebraic definition of simulation between programs. In Proc. Of 2nd Int’l Joint Conf. on Artificial Intelligence, pp 481–489. The British Comp. Soc., 1971.
    • (1971) Proc. Of 2Nd Int’l Joint Conf. On Artificial Intelligence , pp. 481-489
    • Milner, R.1
  • 22
    • 84948983108 scopus 로고    scopus 로고
    • Verification of data-insensitive circuits: An in-orderretirement case study
    • of LNCS, Springer
    • A. Pnueli and T. Arons. Verification of data-insensitive circuits: An in-orderretirement case study. In FMCAD, vol 1522 of LNCS, pp 351–368. Springer, 1998.
    • (1998) FMCAD , vol.1522 , pp. 351-368
    • Pnueli, A.1    Arons, T.2
  • 23
    • 84957377771 scopus 로고    scopus 로고
    • Protocol verification by aggregation of distributed transactions
    • of LNCS, Springer
    • S. Park and D. Dill. Protocol verification by aggregation of distributed transactions. In CAV, vol 1102 of LNCS, pp 300–310. Springer, 1996.
    • (1996) CAV , vol.1102 , pp. 300-310
    • Park, S.1    Dill, D.2
  • 24
    • 0032713341 scopus 로고    scopus 로고
    • Formal verification of anARM processor
    • IEEE; NewYork, NY, January
    • V. Patankar, A. Jain, and R. E. Bryant. Formal verification of anARM processor. In Int’l Conf. on VLSI Design, pp 282–287. IEEE; NewYork, NY, January 1999.
    • (1999) Int’l Conf. On VLSI Design , pp. 282-287
    • Patankar, V.1    Jain, A.2    Bryant, R.E.3
  • 27
    • 0025493701 scopus 로고
    • Formal verification of a pipelined microprocessor
    • September
    • M. Srivas and M. Bickford. Formal verification of a pipelined microprocessor. IEEE Trans. on Software Engineering, pp 52–64, September 1990.
    • (1990) IEEE Trans. On Software Engineering , pp. 52-64
    • Srivas, M.1    Bickford, M.2
  • 28
    • 84947428590 scopus 로고    scopus 로고
    • Trace table based approach for pipelined microprocessor verification
    • of LNCS, Springer
    • J. Sawada and W. Hunt. Trace table based approach for pipelined microprocessor verification. In CAV, vol 1254 of LNCS, pp 364–375. Springer, 1997.
    • (1997) CAV , vol.1254 , pp. 364-375
    • Sawada, J.1    Hunt, W.2
  • 29
    • 84863974979 scopus 로고    scopus 로고
    • Processor verification with precise exceptions and speculative execution
    • of LNCS, Springer
    • J. Sawada and W. Hunt. Processor verification with precise exceptions and speculative execution. In CAV, vol 1427 of LNCS, pp 135–146. Springer, 1998.
    • (1998) CAV , vol.1427 , pp. 135-146
    • Sawada, J.1    Hunt, W.2
  • 30
    • 84958597754 scopus 로고    scopus 로고
    • Results of the verification of a complex pipelined machine model
    • of LNCS, Springer
    • J. Sawada and W. Hunt. Results of the verification of a complex pipelined machine model. In CHARME, vol 1703 of LNCS, pp 313–316. Springer, 1999.
    • (1999) CHARME , vol.1703 , pp. 313-316
    • Sawada, J.1    Hunt, W.2
  • 31
    • 84863960247 scopus 로고    scopus 로고
    • Formal verification of out-of-order execution using incremental flushing
    • of LNCS, Springer
    • J. Skakkebæk, R. Jones, and D. Dill. Formal verification of out-of-order execution using incremental flushing. In CAV, vol 1427 of LNCS, pp 98–109. Springer, 1998.
    • (1998) CAV , vol.1427 , pp. 98-109
    • Skakkebæk, J.1    Jones, R.2    Dill, D.3
  • 32
    • 0029511386 scopus 로고
    • Applying formal verification to a commercial microprocessor
    • August
    • M. K. Srivas and S. P. Miller. Applying formal verification to a commercial microprocessor. In CHDL, pp 493–502, August 1995.
    • (1995) CHDL , pp. 493-502
    • Srivas, M.K.1    Miller, S.P.2
  • 33
    • 84896893786 scopus 로고
    • A correctness model for pipelined microprocessors
    • Springer
    • P. Windley and M. Coe. A correctness model for pipelined microprocessors. In Theorem Provers in Circuit Design, pp 32–51. Springer, 1994.
    • (1994) Theorem Provers in Circuit Design , pp. 32-51
    • Windley, P.1    Coe, M.2


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