A linear array processor with dynamic frequency clocking for image processing applications

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 8, Issue 4, 1998, Pages 435-445

  Ranganathan, N ^a,b   Vijaykrishnan, N ^a,b   Bhavanishankar, N ^b  

^a IEEE   (United States)

^b University of South Florida   (United States)

Author keywords

Dynamic frequency clocking; Image processing architecture; Linear array; SIMD; VLSI

Indexed keywords

COMPUTER ARCHITECTURE; IMAGE COMMUNICATION SYSTEMS; PARALLEL PROCESSING SYSTEMS; PERFORMANCE; REAL TIME SYSTEMS; VLSI CIRCUITS;

DYNAMIC FREQUENCY CLOCKING; LINEAR ARRAY PROCESSOR;

IMAGE PROCESSING;

EID: 0032138398     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/76.709410     Document Type: Article

References (24)

1. G. Even and A. Litman, "Overcoming chip-to-chip delays and clock skews," in Proc. Int. Conf. Application-Specific Syst., Architectures and Processors, 1996, pp. 199-208.
2. C. Nagendra, M. Irwin, and R. Owens, "Area-time-power tradeoffs in parallel adders," IEEE Trans. Circuits Syst. II, vol. 43, pp. 689-702, Oct. 1996.
3. S. Dutta, "VLSI issues for video signal processors," Ph.D. dissertation, Princeton Univ., 1996.
4. N. Ranganathan, N. Vijaykrishnan, and N. Bhavanishankar, "A VLSI array architecture with dynamic frequency clocking," in Proc. Int. Conf. Computer Design, 1996, pp. 137-140.
5. N. Bhavanishankar, "Linear array processor with dynamic frequency clocking," Master's thesis, Univ. South Florida, 1996.
6. Y. Fujita, N. Yamashita, and S. Okazaki, "Compact real-time vision system using integrated memory array processor architecture," IEEE Trans. Circuits Syst. Video Technol., vol. 5, no. 5, pp. 446-452, 1995.
7. M. H. Sunwoo, S. Ong, B. Ahn, and K. Lee, "Design and implementation of a parallel image processor chip for a SIMD array processor," in Proc. Int. Conf. Application-Specific Array Processors, 1995, pp. 66-75.
8. J. Goodenough, R. J. Meacham, J. D. Morris, N. L. Seed, and P. A. Ivey, "Single chip video signal processing architecture for image processing, coding, and computer vision," IEEE Trans. Circuits Syst. Video Technol., vol. 5, no. 5, pp. 436-444, 1995.
9. G. Welch, "A survey of power management techniques in mobile operating systems," Oper. Syst. Rev., vol. 29, pp. 47-56, 1995.
10. H. Kim, M. Irwin, and R. Owens, "MGAP applications in machine perception," in Proc. CAMP'95, Workshop on Computer Architecture for Machine Perception, 1995, pp. 67-73.
11. T. Kelliher, E. Gayles, M. Owens, and J. Irwin, "The MGAP-2: An advanced, massively parallel VLSI signal processor," in Proc. ICASSP, IEEE Int. Conf. Acoust., Speech, Signal Processing, vol. 5, 1995, pp. 3219-3222.
12. E. G. Friedman, Ed., Clock Distribution Networks in VLSI Circuits and Systems. New York: IEEE Press, 1995.
13. I. Page, "The HARP reconfigurable computing system," Oxford University Hardware Compilation Group Rep., 1994.
14. S. Bhandarkar and H. R. Arabnia, "The multi-ring reconfigurable multiprocessor network for computer vision," in Proc. CAMP'93, Workshop on Computer Architectures for Machine Perception, 1993, pp. 180-190.
15. M. Johannesson, A. Astrom, and P. Ingelhag, "The RVIP image processor," in Proc. CAMP'93, Workshop on Computer Architecture for Machine Perception, 1993, pp. 385-393.
16. R. Owens, M. Irwin, C. Nagendra, and R. Bajawa, "Computer vision on the {MGAP}," in Proc. CAMP'93, Workshop on Computer Architectures for Machine Perception, 1993, pp. 337-341.
17. A. L. Fisher and H. T. Kung, "Synchronizing large VLSI processor arrays," IEEE Trans. Comput., vol. C-34, pp. 734-740, Aug. 1985.
18. N. Ranganathan, M. Patel, and P. McCabe, "A two-dimensional systolic array processor for image processing," in Proc. Int. Conf. VLSI Design, India, 1992, vol. 1, pp. 215-220.
19. Y. Fujita, N. Yamashita, and S. Okazaki, "Integrated memory array processor," J. Circuits, Syst., Comput., vol. 2, no. 3, pp. 227-245, 1992.
20. M. Cavaiuolo, A. J. S. Yakovleff, C. R. Watson, and J. A. Kershaw, "A systolic neural network image processing architecture," in Proc. ICASSP, IEEE Int. Conf. Acoust., Speech, Signal Processing, 1992, pp. 695-699.
21. A. Li and S. Kiaei, "VLSI design of multi-rate arrays for DSP algorithms," in ICASSP'90, Int. Conf. Acoust., Speech, Signal Processing, 1990.
22. T. Y. Zhang and C. Y. Suen,"A fast parallel algorithm for thinning digital patterns," Commun. ACM, vol. 27, no. 3, pp. 236-239.
23. W. Hillis, The Connection Machine. Cambridge, MA: M.I.T. Press, 1986.
24. M. J. B. Duff and T. J. Fountain, Computing Structures for Image Processing. New York: Academic, 1983.