Datapath scheduling using dynamic frequency clocking

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Volumn 2002-January, Issue , 2002, Pages 65-70

  Mohanty, S P ^a   Ranganathan, N ^b   Krishna, V ^c  

^a University of South Florida   (United States)

^b UNIVERSITY OF SOUTH FLORIDA   (United States)

^c Agilent Technology   (United States)

Author keywords

Clocks; Delay; Digital to frequency converters; Dynamic scheduling; Frequency; High level synthesis; Scheduling algorithm; Switches; Time factors; Voltage

Indexed keywords

ALGORITHMS; CLOCKS; ELECTRIC POTENTIAL; ENERGY CONSERVATION; HIGH LEVEL SYNTHESIS; INTEGRATED CIRCUIT TESTING; SCHEDULING; SWITCHES; SYNTHESIS (CHEMICAL); TIME SWITCHES;

BENCHMARK CIRCUIT; CRITICAL PATH DELAYS; DATAPATH SCHEDULING; DELAY; DYNAMIC SCHEDULING; FREQUENCY; HIGHER FREQUENCIES; TIME FACTORS;

SCHEDULING ALGORITHMS;

EID: 84948659051     PISSN: 21593469     EISSN: 21593477     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2002.1016876     Document Type: Conference Paper

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