A heterogeneous 3D-IC consisting of two 28 nm FPGA die and 32 reconfigurable high-performance data converters

IEEE Journal of Solid-State Circuits

Volumn 50, Issue 1, 2015, Pages 258-269

  Erdmann, Christophe ^a   Lowney, Donnacha ^a   Lynam, Adrian ^a   Keady, Aidan ^a   McGrath, John ^a   Cullen, Edward ^a   Breathnach, Daire ^a   Keane, Denis ^a   Lynch, Patrick ^a   De La Torre, Marites ^a   De La Torre, Ronnie ^a   Lim, Peng ^a   Collins, Anthony ^a   Farley, Brendan ^a   Madden, Liam ^a  

^a XILINX INC   (United States)

Author keywords

2.5D; 3D IC; ADC; analog; CMOS; DAC; data converter; FPGA; heterogeneous; high performance; low power; reconfigurable; SSI

Indexed keywords

DIES; DIGITAL TO ANALOG CONVERSION; LOGIC DEVICES; THREE DIMENSIONAL INTEGRATED CIRCUITS;

CURRENT STEERING; DIGITAL TO ANALOG; HIGH DENSITY INTERCONNECTS; NOISE ISOLATION; PERFORMANCE DATA; PIPELINED ADCS; RECONFIGURABLE; SYSTEM PARTITIONING;

RECONFIGURABLE HARDWARE;

EID: 84936760362     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2014.2357432     Document Type: Article

References (18)

1. D. Maheshwari, "Memory and system architecture for 400 Gb/s net working and beyond, " in IEEE ISSCC Dig. Tech. Papers, 2014, pp. 116-117.
2. C. Erdmann et al., "A heterogeneous 3D-IC consisting of two 28 nm FPGA die and 32 reconfigurable high-performance data converters, " in IEEE ISSCC Dig. Tech. Papers, 2014, pp. 120-121.
3. L. Madden et al., "Advancing high performance heterogeneous integration through die stacking, " in Proc. ESSCIRC, 2012, pp. 18-24.
4. N. Kim et al., "Through Silicon Via (TSV) design considering technology challenges for very high-speed signal transmission, " in Proc. DesignCon, 2011, vol. 2, pp. 1601-1622.
5. S. Uemura, "Isolation techniques against substrate noise coupling utilizing Through Silicon Via (TSV) process for RF/mixed-signal SoCs, " IEEE J. Solid-State Circuits, vol. 47, no. 4, pp. 810-816, Apr. 2012.
6. T. Ito et al., "55-mW 1.2 V 12-bit 100-MSPS pipeline ADCs for wireless receivers, " in Proc. ESSCIRC, 2006, pp. 540-543.
7. T.-N. Andersen et al., "A cost efficient high speed 12-bit pipeline ADC in 0.18 m digital CMOS, " IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1506-1513, Jul. 2005.
8. A. Siragusa and I. Galton, "A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC, " IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2126-2138, Dec. 2004.
9. K. Doris, A. van Roermund, and D. Leenaerts, Wide-Bandwidth High Dynamic Range D/A Converters. New York, NY, USA: Springer, 2006.
10. A. Van den Bosch, M. Steyaert, and W. Sansen, Static and Dynamic Performance Limitations for High Speed D/A Converters. Boston, MA, USA: Kluwer, 2004.
11. P. Quinn, H. Hegt, and A. van Roermund, Smart and Flexible Dig ital-to-Analog Converters. New York, NY, USA: Springer, 2011.
12. M. Pelgrom, A. Duinmaijer, and A. Welbers, "Matching properties of MOS transistors, " IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433-1440, 1989.
13. G. Van der Plas et al., "A 14-bit intrinsic accuracy Q2 random walk CMOS DAC, " IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1708-1718, 1999.
14. T. Miki et al., "An 80-MHz 8-bit CMOS D/A converter, " IEEE J. Solid-State Circuits, vol. SC-21, no. 6, pp. 983-988, 1986.
15. J. Kanatharana et al., "Examination of mechanical stresses in silicon substrates due to lead-tin solder bumps via micro-Raman spectroscopy and finite element modelling, " Semicond. Sci. Technol., vol. 17, pp. 1255-1260, 2002.
16. N. Kurosawa et al., "Explicit analysis of channel mismatch effects in time-interleaved ADC systems, " IEEE Trans. Circuits Syst. I, vol. 48, no. 3, pp. 261-271, 2001.
17. C. H. Lin et al., "A 12 bit 2.9 GS/s DAC with IM3 60 dBc beyond 1 GHz in 65 nm CMOS, " IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3285-3293, 2009.
18. J.-W. Nam et al., "A 12-bit 100-MS/s pipelined ADC in 45 nm CMOS, " in Proc. SoC Design Conf. (ISOCC), 2011, pp. 405-407.