A heterogeneous 3D-IC consisting of two 28nm FPGA die and 32 reconfigurable high-performance data converters

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 57, Issue , 2014, Pages 120-121

  Erdmann, Christophe ^a   Lowney, Donnacha ^a   Lynam, Adrian ^a   Keady, Aidan ^a   McGrath, John ^a   Cullen, Edward ^a   Breathnach, Daire ^a   Keane, Denis ^a   Lynch, Patrick ^a   De La Torre, Marites ^a   De La Torre, Ronnie ^a   Lim, Peng ^a   Collins, Anthony ^a   Farley, Brendan ^a   Madden, Liam ^a  

^a XILINX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA HANDLING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

DATA CONVERSION; DATA CONVERTER; DISCRETE DEVICES; DIVERSE APPLICATIONS; EXPONENTIAL GROWTH; IO INTERFACES; POWER EFFICIENT; RECONFIGURABLE;

RECONFIGURABLE HARDWARE;

EID: 84898079667     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2014.6757364     Document Type: Conference Paper

References (6)

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2. M. Santarini, "Stacked & Loaded", XCell Journal, pp. 8-13, Q1-2011.
3. C-H. Lin, et al., "A 12b 2.9GS/s DAC with IM3 <-60dBc Beyond 1GHz in 65nm CMOS", ISSCC Dig. Tech. Papers, pp. 74-75, Feb. 2009.
4. K. Doris, et al., "A 12b 500MS/s DAC with >70dB SFDR up to 120MHz in 0.18μm CMOS", ISSCC Dig. Tech. Papers, pp. 116-117, Feb. 2005.
5. J-W. Nam, et al., "A 12-bit 100-MS/s pipelined ADC in 45nm CMOS", SoC Design Conference (ISOCC), pp. 405-407, 2011.
6. T-N Andersen, et al., "A cost-efficient high-speed 12-bit pipeline ADC in 0.18ìm digital CMOS", IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1506-1513, 2005.