A 12 bit 2.9 GS/s DAC with IM3 < 60 dBc beyond 1 GHz in 65 nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 12, 2009, Pages 3285-3293

  Lin, Chi Hung ^a   Van Der Goes, Frank M L ^b   Westra, Jan R ^b   Mulder, Jan ^b   Lin, Yu ^b   Arslan, Erol ^b   Ayranci, Emre ^b   Liu, Xiaodong ^b   Bult, Klaas ^b  

^a BROADCOM CORPORATION   (United States)

^b Broadcom   (Netherlands)

Author keywords

CMOS; Current steering; D A converters; Digital to analog converter (DAC); Full Nyquist; HD3; High frequency; High speed; IM3

Indexed keywords

CURRENT-STEERING D/A CONVERTER; DIGITAL-TO-ANALOG CONVERTER (DAC); DIGITAL-TO-ANALOG CONVERTERS; FULL NYQUIST; HIGH FREQUENCY;

ELECTRIC CURRENTS; HYBRID COMPUTERS;

DIGITAL INTEGRATED CIRCUITS;

EID: 72949118715     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2032624     Document Type: Conference Paper

References (13)

1. H. J. Schouwenaars, D. W. J. Groeneveld, C. A. A. Bastiaansen, and H. A. H. Termeer, "An oversampled multi-bit CMOS D/A converter for digital audio with 115-dB dynamic range," IEEE J. Solid-State Circuits, vol.26, no.12, pp. 1775-1780, Dec. 1991.
2. 2 ," IEEE J. Solid-State Circuits, vol.33, no.12, pp. 1948-1958, Dec. 1998.
3. K. Bult and C.-H. Lin, "Digital to analog converter with reduced ringing," U.S. 6,191,719, Feb. 20, 2001.
4. A. Van den Bosch et al., "A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter," IEEE J. Solid-State Circuits, vol.36, no.3, pp. 315-324, Mar. 2001.
5. B. Schafferer and R. Adams, "A 3 V CMOS 400 mW 14 b 1.4 GS/s DAC for multi-carrier applications," in IEEE ISSCC Dig. Tech. Papers, Feb. 2004, pp. 360-361.
6. W. Schofield et al., "A 16 b 400 MS/s DAC with < -80 dBc IMD to 300 MHz and < -160 dBm/Hz noise power spectral density," in IEEE ISSCC Dig. Tech. Papers, Feb. 2003, pp. 126-127.
7. K. Doris et al., "A 12 b 500 MS/s DAC with > 70 dB SFDR up to 120 MHz in 0.18μm CMOS," in IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp. 116-117.
8. D. A. Mercer, "Low-power approaches to high-speed current-steering digital-to-analog converters in 0.18-μm CMOS," IEEE J. Solid-State Circuits, vol.42, pp. 1688-1698, Aug. 2007.
9. P. Palmers and M. Steyeart, "A 11 mW 68 dB SFDR 100 MHz bandwidth SD-DAC based on a 5-bit 1 GS/s core in 130 nm," in Proc. ESSCIRC, Sep. 2008, pp. 214-217.
10. M. Pelgrom, A. Duinmaijer, and A. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol.SC-24, pp. 1433-1439, Oct. 1989.
11. K. L. Chan, J. Zhu, and I. Galton, "Dynamic element matching to prevent nonlinear distortion from pulse-shape mismatches in high-resolution DACs," IEEE J. Solid-State Circuits, vol.43, pp. 2067-2078, Sep. 2008.
12. T. Miki et al., "An 80-MHz 8-bitCMOSD/A converter," IEEE J. Solid-State Circuits, vol.SC-21, no.6, pp. 983-988, Dec. 1986.
13. J. T. Stonick et al., "An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-μm CMOS," IEEE J. Solid-State Circuits, vol.38, no.3, pp. 436-443, Mar. 2003.