-
1
-
-
84934327125
-
-
http://www. amd. com/us/products/server/processors/6000-seriesplatform/ 6300/Pages/6300-series-processors. aspx#2
-
-
-
-
2
-
-
84872067428
-
-
Intel. Intel Core i7 Processor. http://www. intel. com/products/processor/ corei7/specifications. htm
-
Intel Core i7 Processor
-
-
-
3
-
-
84934327126
-
-
http://blog. stuffedcow. net/2013/01/ivb-cache-replacement/
-
-
-
-
4
-
-
84934327127
-
-
http://www. hotchips. org/wp-content/uploads/hcárchives/hc24/HC24-1-Microprocessor/HC24. 28. 117-HotChips-IvyBridge-Power-04. pdf
-
-
-
-
5
-
-
84934327128
-
-
http://www. jilp. org/dpc/ (Commercial workload targeted prefetcher was not in the top three performing prefetchers across several server, multimedia, games, scientific, and engineering workloads.)
-
-
-
-
6
-
-
84934327129
-
-
http://www. hpl. hp. com/research/cacti/
-
-
-
-
7
-
-
0023672138
-
On the inclusion properties for multi-level cache hierarchies
-
J. L. Baer and W. Wang. "On the Inclusion Properties for Multi-level Cache Hierarchies. " In ISCA, 1988.
-
(1988)
ISCA
-
-
Baer, J.L.1
Wang, W.2
-
8
-
-
0031594023
-
Memory system characterization of commercial workloads
-
L. Barroso, K. Gharachorloo, E. Bugnion. "Memory System Characterization of Commercial Workloads" In ISCA, 1998.
-
(1998)
ISCA
-
-
Barroso, L.1
Gharachorloo, K.2
Bugnion, E.3
-
9
-
-
34548008288
-
ASR: Adaptive selection replication for cmp caches
-
B. Beckmann, M. Marty, D. Wood. "ASR: Adaptive Selection Replication for CMP Caches. " In MICRO, 2006.
-
(2006)
MICRO
-
-
Beckmann, B.1
Marty, M.2
Wood, D.3
-
10
-
-
33845903561
-
Cooperative caching for chip multiprocessors
-
J. Chang and G. S. Sohi. "Cooperative Caching for Chip Multiprocessors". In ISCA'2006.
-
ISCA'2006
-
-
Chang, J.1
Sohi, G.S.2
-
12
-
-
84858791438
-
Clearing the clouds: A study of emerging scale-out workloads on modern hardware
-
M. Ferdman et al. "Clearing the Clouds: A Study of Emerging Scale-out Workloads on Modern Hardware. " In ASPLOS 2012.
-
(2012)
ASPLOS
-
-
Ferdman, M.1
-
15
-
-
79951707365
-
Techniques for reducing the impact of inclusion in shared network cache multiprocessors
-
K. Fletcher, W. E. Speight, and J. K. Bennett. "Techniques for Reducing the Impact of Inclusion in Shared Network Cache Multiprocessors. " Rice ELEC TR 9413, 1995.
-
(1995)
Rice ELEC TR 9413
-
-
Fletcher, K.1
Speight, W.E.2
Bennett, J.K.3
-
16
-
-
80052536606
-
Bypass and insertion algorithms for exclusive last-level caches
-
J. Gaur, M. Chaudhuri, and S. Subramoney. "Bypass and Insertion Algorithms for Exclusive Last-Level Caches". In ISCA 2011.
-
(2011)
ISCA
-
-
Gaur, J.1
Chaudhuri, M.2
Subramoney, S.3
-
17
-
-
84863354514
-
Database servers on chip multiprocessors: Limitations & opportunities
-
Jan'07
-
N. Hardavellas et al. "Database servers on chip multiprocessors: limitations & opportunities". Innovative Data Systems Research, Jan'07.
-
Innovative Data Systems Research
-
-
Hardavellas, N.1
-
18
-
-
34548288510
-
The AMD Athlon XP Processor with 512KB L2 Cache
-
J. Huynh. "The AMD Athlon XP Processor with 512KB L2 Cache". White Paper, 2003.
-
(2003)
White Paper
-
-
Huynh, J.1
-
19
-
-
77949710964
-
CMPim: A pin-based on-the-fly multi-core cache simulator
-
A. Jaleel, R. Cohn, C. K. Luk, B. Jacob. CMPim: A Pin-Based On-The-Fly Multi-Core Cache Simulator. In MoBS, 2008.
-
(2008)
MoBS
-
-
Jaleel, A.1
Cohn, R.2
Luk, C.K.3
Jacob, B.4
-
20
-
-
77954998134
-
High performance cache replacement using re-reference interval prediction (RRIP)
-
A. Jaleel, K. Theobald, S. Steely, and J. Emer. "High Performance Cache Replacement Using Re-Reference Interval Prediction (RRIP)". ISCA'10.
-
ISCA'10
-
-
Jaleel, A.1
Theobald, K.2
Steely, S.3
Emer, J.4
-
21
-
-
63549149925
-
Adaptive insertion policies for managing shared caches
-
A. Jaleel, W. Hasenplaugh, M. K. Qureshi, J. Sebot, S. Steely, and J. Emer. "Adaptive Insertion Policies for Managing Shared Caches". In PACT, 2008.
-
(2008)
PACT
-
-
Jaleel, A.1
Hasenplaugh, W.2
Qureshi, M.K.3
Sebot, J.4
Steely, S.5
Emer, J.6
-
22
-
-
79951719036
-
Achieving non-inclusive cache performance with inclusive caches-temporal locality aware (TLA) cache management policies
-
A. Jaleel, E. Borch, M. Bhandaru, S. Steely, and J. Emer. "Achieving Non-Inclusive Cache Performance with Inclusive Caches-Temporal Locality Aware (TLA) Cache Management Policies". In MICRO 2010.
-
(2010)
MICRO
-
-
Jaleel, A.1
Borch, E.2
Bhandaru, M.3
Steely, S.4
Emer, J.5
-
24
-
-
0028201665
-
Tradeoffs in two-level on-chip caching
-
N. Jouppi, and S. E. Wilton. "Tradeoffs in two-level on-chip caching. " ISCA'94
-
ISCA'94
-
-
Jouppi, N.1
Wilton, S.E.2
-
25
-
-
0025429331
-
Improving direct-mapped cache performance by the addition of a fully associative cache and prefetch buffers
-
N. P. Jouppi. "Improving direct-mapped cache performance by the addition of a fully associative cache and prefetch buffers. " ISCA, 1990.
-
(1990)
ISCA
-
-
Jouppi, N.P.1
-
27
-
-
85088081337
-
Cache replacement with dynamic exclusion
-
S. McFarling. "Cache Replacement with Dynamic Exclusion. " ISCA'92.
-
ISCA'92
-
-
McFarling, S.1
-
28
-
-
84879857744
-
Scale-out processors
-
P. L-Kamran, et al. "Scale-Out Processors". In ISCA'12.
-
ISCA'12
-
-
L-Kamran, P.1
-
30
-
-
85102095116
-
Adaptive spill-receive for robust high-performance caching in CMPs
-
M. K. Qureshi. "Adaptive Spill-Receive for Robust High-Performance Caching in CMPs". In HPCA'2009.
-
HPCA'2009
-
-
Qureshi, M.K.1
-
31
-
-
21644454187
-
Pinpointing representative portions of large intel itanium programs with dynamic instrumentation
-
H. Patil, R. Cohn, M. Charney, R. Kapoor, and A. Sun. "Pinpointing Representative Portions of Large Intel Itanium Programs with Dynamic Instrumentation. " In MICRO 2004.
-
(2004)
MICRO
-
-
Patil, H.1
Cohn, R.2
Charney, M.3
Kapoor, R.4
Sun, A.5
-
32
-
-
84934327137
-
Optimizations enabled by a decoupled front-end architecture
-
G. Reinman, B. Calder, and T. Austin. "Optimizations Enabled by a Decoupled Front-End Architecture. " In TOCS, 2001.
-
(2001)
TOCS
-
-
Reinman, G.1
Calder, B.2
Austin, T.3
-
33
-
-
84864858369
-
FLExclusion: Balancing cache capacity and on-chip bandwidth via flexible exclusion
-
J. Sim, et al. "FLEXclusion: Balancing Cache Capacity and On-Chip Bandwidth via Flexible Exclusion. " In ISCA'12.
-
ISCA'12
-
-
Sim, J.1
-
35
-
-
84934327140
-
Practical off-chip meta-data for temporal memory streaming
-
T. Wenisch, et al. "Practical Off-Chip Meta-Data for Temporal Memory Streaming. " In HPCA'09.
-
HPCA'09
-
-
Wenisch, T.1
-
36
-
-
84863389330
-
SHiP: Signature-based hit predictor for high performance caching
-
C. Wu, A. Jaleel, W. Hasenplaugh, M. Martonosi, S. Steely, and J. Emer. "SHiP: Signature-based Hit Predictor for High Performance Caching. " In MICRO 2011.
-
(2011)
MICRO
-
-
Wu, C.1
Jaleel, A.2
Hasenplaugh, W.3
Martonosi, M.4
Steely, S.5
Emer, J.6
-
37
-
-
84863379287
-
PACMan: Prefetch-aware cache management for high performance caching
-
C. Wu, A. Jaleel, M. Martonosi, S. Steely, and J. Emer. "PACMan: Prefetch-Aware Cache Management for High Performance Caching. " In MICRO 2011.
-
(2011)
MICRO
-
-
Wu, C.1
Jaleel, A.2
Martonosi, M.3
Steely, S.4
Emer, J.5
-
38
-
-
70449695861
-
Non-inclusion property in multi-level caches revisited
-
M. Zahran. "Non-inclusion property in multi-level caches revisited. ", in IJCA'07, 2007.
-
(2007)
IJCA'07
-
-
Zahran, M.1
-
39
-
-
84867544225
-
Cache replacement policy revisited
-
M. Zahran. "Cache Replacement Policy Revisited. ", WDDD, 2007.
-
(2007)
WDDD
-
-
Zahran, M.1
-
40
-
-
2642545887
-
Performance evaluation of exclusive cache hierarchies
-
Y. Zheng, B. T. Davis, and M. Jordan. "Performance Evaluation of Exclusive Cache Hierarchies. " In ISPASS, 2004.
-
(2004)
ISPASS
-
-
Zheng, Y.1
Davis, B.T.2
Jordan, M.3
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