OS-controlled cache predictability for real-time systems

Real-Time Technology and Applications - Proceedings

Volumn , Issue , 1997, Pages 213-223

  Liedtke, Jochen ^a,b   Hartig, Hermann ^c   Hohmuth, Michael ^c  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b FRAUNHOFER INSTITUTE FOR APPLIED INFORMATION TECHNOLOGY FIT   (Germany)

^c DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE ARCHITECTURE; CACHE STRUCTURE; CRITICAL PATHS; FILTER ALGORITHM; MODERN PROCESSORS; WORKING SET; WORST-CASE EXECUTION;

ALGORITHMS; PROGRAM PROCESSORS; REAL TIME SYSTEMS; BUFFER STORAGE; COMPUTER ARCHITECTURE; PREDICTIVE CONTROL SYSTEMS;

CACHE MEMORY; REAL TIME SYSTEMS;

CACHE PARTITIONING TECHNIQUES; MEMORY COLORING TECHNIQUES; WORST CASE PENALTIES;

EID: 0031348717     PISSN: 10801812     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTTAS.1997.601360     Document Type: Conference Paper

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