Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2014, Pages 84-95

  Agrawal, Aditya ^a   Ansari, Amin ^a,b   Torrellas, Josep ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b QUALCOMM INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELLS; COMPUTER ARCHITECTURE; ENERGY UTILIZATION; SUPERCOMPUTERS;

CACHE CONTROLLER; LAST-LEVEL CACHES; PROCESS VARIATION; RETENTION PROPERTIES; RETENTION TIME; SPATIAL CORRELATIONS; SPATIAL LOCALITY; SUBSTANTIAL ENERGY;

CYTOLOGY;

EID: 84904007750     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2014.6835978     Document Type: Conference Paper

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