Redundancy techniques for high-density DRAMs

Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon

Volumn , Issue , 1997, Pages 22-29

  Horiguchi, Masashi ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR ARRAYS; COMPUTER ARCHITECTURE; ELECTRIC FAULT CURRENTS; INTEGRATED CIRCUIT LAYOUT; REDUNDANCY; SEMICONDUCTOR STORAGE;

DYNAMIC RANDOM ACCESS MEMORY (DRAM);

RANDOM ACCESS STORAGE;

EID: 0031383328     PISSN: 10632204     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)