Nanoelectronic SET-based core for network-on-chip architectures

Microelectronics Journal

Volumn 45, Issue 7, 2014, Pages 972-975

  Pes B S ^a   Guimaraes J G ^a   Da Costa, J C ^a  

^a UNIVERSITY OF BRASILIA   (Brazil)

Author keywords

Nanoelectronic; Network on chip; Performance; Single electron transistor

Indexed keywords

CAPACITANCE MEASUREMENT; MICROELECTRONICS; NANOELECTRONICS; QUANTUM THEORY; SERVERS; SINGLE ELECTRON TRANSISTORS; VLSI CIRCUITS;

ARITHMETIC LOGIC UNIT; CLOCK FREQUENCY; NETWORK-ON-CHIP ARCHITECTURES; NETWORK-ON-CHIP(NOC); NOC ARCHITECTURES; ORDERS OF MAGNITUDE; PERFORMANCE; QUANTUM-MECHANICAL DEVICES;

NETWORK-ON-CHIP;

EID: 84902381082     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2013.12.008     Document Type: Article

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