An accurate model for dynamic crosstalk analysis of CMOS gate driven on-chip interconnects using FDTD method

Microelectronics Journal

Volumn 45, Issue 4, 2014, Pages 441-448

  Kumar, Vobulapuram Ramesh ^a   Kaushik, Brajesh Kumar ^a   Patnaik, Amalendu ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY ROORKEE   (India)

Author keywords

CMOS; Coupled interconnect lines; Dynamic crosstalk; FDTD; Transient analysis

Indexed keywords

CMOS INTEGRATED CIRCUITS; CROSSTALK; DATA COMMUNICATION EQUIPMENT; TIME DOMAIN ANALYSIS; TRANSIENT ANALYSIS;

ACCURATE MODELING; DYNAMIC CROSSTALK; FINITE DIFFERENCE TIME DOMAIN TECHNIQUE; HSPICE SIMULATIONS; INTERCONNECT LINES; ON-CHIP INTERCONNECTS; PROPAGATION DELAYS; RLC INTERCONNECTS;

FINITE DIFFERENCE TIME DOMAIN METHOD;

EID: 84899977509     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2014.02.004     Document Type: Article

References (17)

1. J.M. Rabaey, A. Chandrakasan, and B. Nikolic Digital Integrated Circuits, A Design Perspective second ed. 2003 Prentice-Hall
2. B.K. Kaushik, S. Sarkar, R.P. Agarwal, and R.C. Joshi An analytical approach to dynamic crosstalk in coupled interconnects Microelectron. J. 41 2010 85 92
3. C.J. Alpert, A. Devgan, and C.V. Kashyap RC delay metrics for performance optimization IEEE Trans. Comput. Adied Des. Integr. Circuits Syst. 20 2001 571 582 (Pubitemid 32518570)
4. J. Rubinstein, P. Penfield, and M.A. Horowitz Signal delay in RC tree networks IEEE Trans. Comput.Aided Des. Integr. Circuits Syst. 2 1983 202 211
5. M. Masoumi, N. Masoumi, and A. Javanpak A new and efficient approach for estimating the accurate time-domain response of single and capacitive coupled distributed RC interconnects Microelectron. J. 40 2009 1212 1224
6. Y.I. Ismail, E.G. Friedman, and J.L. Neves Equivalent elmore delay for RLC trees IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 2000 83 97 (Pubitemid 30557236)
7. K. Agarwal, D. Sylvester, and D. Blaauw Modeling and analysis of crosstalk noise IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 2006 892 901
8. W. Ding, and G. Wang Analytical timing model for inductance-dominant interconnect based on traveling wave propagation Microelectron. J. 40 2009 905 911
9. T. Liu, J. Kuo, S. Zhang, and A. Closed-Form Analytical transient response model for on-chip distortionless interconnect IEEE Trans. Electron Devices 59 2012 3186 3192
10. B.K. Kaushik, and S. Sarkar Crosstalk analysis for a CMOS gate driven inductively and capacitively coupled interconnects Microelectron. J. 39 2008 1834 1842
11. X. Li, J. Mao, J. Mao, and M. Swaminathan Transient analysis of CMOS-gate-driven RLGC interconnects based on FDTD IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 2011 574 583
12. T. Sakurai, and R. Newton Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas IEEE J. Solid-State Circuits 25 1990 584 594 (Pubitemid 20701405)
13. C.R. Paul Incorporation of terminal constraints in the FDTD analysis of transmission lines IEEE Trans. Electromagn. Compat. 36 1994 85 91
14. A. Taflove Review of the formulation and applications of the finite-difference time-domain method for numerical modeling of electromagnetic wave interactions with arbitrary structures Spec. Issue Numer. Methods Electromagn. Wave Interact. 10 1988 547 582
15. C.R. Paul Analysis of Multiconductor Transmission Lines 2008 IEEE Press New Jersey
16. A. Naeemi, and J.D. Meindl Design and performance modeling for single-walled carbon nanotubes as local, semiglobal, and global interconnects in gigascale integrated systems IEEE Trans. Electron Devices 54 2007 26 37 (Pubitemid 46056039)
17. J.A. Davis, and J.D. Meindl Compact distributed RLC interconnect models - Part II□: coupled line transient expressions and peak crosstalk in multilevel networks IEEE Trans. Electron Devices 47 2000 2078 2087.