An analytical approach to dynamic crosstalk in coupled interconnects

Microelectronics Journal

Volumn 41, Issue 2-3, 2010, Pages 85-92

  Kaushik, Brajesh Kumar ^a   Sarkar, Sankar ^b   Agarwal, Rajendra Prasad ^b   Joshi, R C ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY ROORKEE   (India)

^b SHOBHIT UNIVERSITY   (India)

Author keywords

Coupled transmission lines; Crosstalk; Interconnections; Signal integrity; VLSI CAD

Indexed keywords

ALPHA-POWER LAW; ANALYTICAL APPROACH; CMOS DRIVER; CMOS GATE; COUPLED INTERCONNECTS; COUPLED MODELS; COUPLED TRANSMISSION LINE; COUPLED TRANSMISSION LINES; DELAY ESTIMATION; DYNAMIC CROSSTALK; IN-PHASE; INDUCTIVELY-COUPLED; MOS TRANSISTORS; OUT OF PHASE; PEAK ESTIMATION; PROPAGATION DELAYS; SIGNAL INTEGRITY; SPICE SIMULATIONS; TRANSITION TIME; TRANSMISSION LINE; VLSI CAD; WAVEFORM SHAPE;

BANDPASS FILTERS; ELECTRIC LINES; SUPERALLOYS; TIME DELAY; TRANSISTOR TRANSISTOR LOGIC CIRCUITS; TRANSMISSION LINE THEORY;

CROSSTALK;

EID: 77649338408     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2009.12.011     Document Type: Article

References (23)

1. Rabaey J.M. Digital Integrated Circuits, A Design Perspective (1996), Prentice-Hall, Englewood Cliffs, NJ
2. D.A. Priore, Inductance on silicon for sub-micron CMOS VLSI, in: Proceedings of the IEEE Symposium VLSI Circuits, May 1993, pp. 17-18.
3. Deutsch, G.V. Kopcsay, P. Restle, G. Katopis, W.D. Becker, H. Smith, P.W. Coteus, C.W. Surovic, B.J. Rubin, R.P. Dunne, T. Gallo, K.A. Jenkins, L.M. Terman, R.H. Dennard, G.A. Sai-Halasz, D.R. Knebel, When are transmission-line effects important for on-chip interconnections, in: Proceedings of the Electronic Components Technology Conference, May 1997, pp. 704-712.
4. Y.I. Ismail, E.G. Friedman, J.L. Neves, Figures of merit to characterize the importance of on-chip inductance, in: IEEE Transactions on VLSI Systems, vol. 7, pp. 442-449, Dec 1999.
5. Eo Y., and Eisenstadt W.R. High-speed VLSI interconnect modeling based on S-parameter measurement. IEEE Trans. Comp., Hybrids, Manufact. Technol. 16 (Aug. 1993) 555-562
6. Shoji M. High-speed Digital Circuits (1996), Addison-Wesley, Reading, MA
7. Venkatesan R., Davis J.A., and Meindl J.D. Compact distributed RLC interconnect models-Part III: Transients in single and coupled lines with capacitive load termination. IEEE Trans. ED 50 (2003) 1081-1093
8. Banerjee K., and Mehrotra A. Analysis of on-chip inductance effects for distributed RLC interconnects. IEEE Trans. on CAD 21 (2002) 904-915
9. Davis J.A., and Meindl J.D. Compact distributed RLC interconnect models-Part I: Single line transient, time delay and overshoot expressions. IEEE Trans. ED 47 (Nov. 2000) 2068-2077
10. Davis J.A., and Meindl J.D. Compact distributed RLC interconnect models-Part II: Coupled line transient expressions and peak crosstalk in multilevel interconnect networks. IEEE Trans. ED 47 (Nov. 2000) 2078-2087
11. Agarwal K., Sylvester D., and Blaauw D. Modeling and analysis of crosstalk noise in coupled RLC interconnects. IEEE Trans. CAD Integr. Circuits Syst. 25 (May 2006) 892-901
12. Sakurai T., and Newton A.R. Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. IEEE J. Solid-State Circuits 25 (Apr. 1990) 584-594
13. Sakurai T. Closed form expressions for interconnection delay, coupling and crosstalk in VLSI's. IEEE Trans. ED 40 (Jan. 1993) 118-124
14. D. Sylvester, K. Shepard, Electrical integrity design and verification for digital and mixed-signal systems on a chip, in: Tutorial-International Conference on Computer Aided Design, San Jose, CA, Nov. 2001.
15. Vittal A., Chen L., Marek-Sadowska M., Wang K.P., and Yang S. Crosstalk in VLSI interconnections. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 18 2 (Dec. 1999) 1817-1824
16. K.L. Shepard, V. Narayanan, Noise in deep submicron digital design, in: Proceedings of the International Conference on Computer-Aided Design, San Jose, CA, 1996, 524-531 pp.
17. Tang K.T., and Friedman E.G. Peak crosstalk noise estimation in CMOS VLSI circuit. Proc. ICECS 3 (1999) 1539-1542
18. Davis J.A., and Meindl J.D. Compact distributed RLC interconnect models-Part I: Single line transient, time delay and overshoot expressions. IEEE Trans. ED. 47 (Nov. 2000) 2068-2077
19. Davis J.A., and Meindl J.D. Compact distributed RLC interconnect models-Part II: Coupled line transient expressions and peak crosstalk in multilevel interconnect networks. IEEE Trans. ED. 47 (Nov. 2000) 2078-2087
20. Venkatesan R., Davis J.A., and Meindl J.D. Compact distributed RLC interconnect models-Part III: Transients in single and coupled lines with capacitive load termination. IEEE Trans. ED. 50 (Apr. 2003) 1081-1093
21. Venkatesan R., Davis J.A., and Meindl J.D. Compact distributed RLC interconnect models-Part IV: Unified models for time delay, crosstalk, and repeater insertion. IEEE Trans. ED. 50 (Apr. 2003) 1094-1102
22. Gupta K.C. Microstrip Lines and Slotlines (1996), Artech House, Norwood, MA
23. Kaushik B.K., and Sarkar S. Crosstalk analysis for a CMOS gate driven inductively and capacitively coupled interconnects. Microelectronics Journal 39 (2008) 1834-1842