-
2
-
-
35748932911
-
Nanoelectronics from the bottom up
-
DOI 10.1038/nmat2028, PII NMAT2028
-
W. Lu and C. Lieber, "Nanoelectronics from the bottom up," Nat. Mater., vol. 6, no. 11, pp. 841-850, 2007. (Pubitemid 350050579)
-
(2007)
Nature Materials
, vol.6
, Issue.11
, pp. 841-850
-
-
Lu, W.1
Lieber, C.M.2
-
3
-
-
33748989811
-
CMOL: Devices, circuits, and architectures
-
DOI 10.1007/3-540-31514-4-17, Introducing Molecular Electronics
-
K. Likharev and D. Strukov, "CMOL: devices, circuits, and architectures," Introducing Mol. Electron., vol. 680, pp. 447-477, 2005. (Pubitemid 44445609)
-
(2006)
Lecture Notes in Physics
, vol.680
, pp. 447-477
-
-
Likharev, K.K.1
Strukov, D.B.2
-
4
-
-
16244389374
-
Computing with hysteretic resistor crossbars
-
DOI 10.1007/s00339-004-3149-1, Nanoelectronics
-
G. Snider, "Computing with hysteretic resistor crossbars," Appl. Phys. A, Mater. Sci. Process., vol. 80, no. 6, pp. 1165-1172, 2005. (Pubitemid 40454134)
-
(2005)
Applied Physics A: Materials Science and Processing
, vol.80
, Issue.6
, pp. 1165-1172
-
-
Snider, G.1
-
5
-
-
13644283486
-
The crossbar latch: Logic value storage, restoration, and inversion in crossbar circuits
-
P. Kuekes, D. Stewart, and R. Williams, "The crossbar latch: Logic value storage, restoration, and inversion in crossbar circuits," J. Appl. Phys., vol. 97, no. 3, pp. 034 301.1-034 301.5, 2005.
-
(2005)
J. Appl. Phys
, vol.97
, Issue.3
, pp. 0343011-0343015
-
-
Kuekes, P.1
Stewart, D.2
Williams, R.3
-
6
-
-
43049126833
-
The missing memristor found
-
DOI 10.1038/nature06932, PII NATURE06932
-
D. Strukov, G. Snider, D. Stewart, and R. Williams, "The missing memristor found," Nature, vol. 453, no. 7191, pp. 80-83, 2008. (Pubitemid 351630336)
-
(2008)
Nature
, vol.453
, Issue.7191
, pp. 80-83
-
-
Strukov, D.B.1
Snider, G.S.2
Stewart, D.R.3
Williams, R.S.4
-
7
-
-
35748974883
-
Nanoionics-based resistive switchingmemories
-
R. Waser and M. Aono, "Nanoionics-based resistive switchingmemories," Nat. Mater., vol. 6, no. 11, pp. 833-840, 2007.
-
(2007)
Nat. Mater
, vol.6
, Issue.11
, pp. 833-840
-
-
Waser, R.1
Aono, M.2
-
8
-
-
67650102619
-
Redox-based resistive switching memories-nanoionic mechanisms, prospects, and challenges
-
R. Waser, R. Dittmann, G. Staikov, and K. Szot, "Redox-based resistive switching memories-nanoionic mechanisms, prospects, and challenges," Adv. Mater., vol. 21, nos. 25-26, pp. 2632-2663, 2009.
-
(2009)
Adv. Mater
, vol.21
, Issue.25-26
, pp. 2632-2663
-
-
Waser, R.1
Dittmann, R.2
Staikov, G.3
Szot, K.4
-
9
-
-
20444372632
-
Nanoscale memory elements based on solid-state electrolytes
-
DOI 10.1109/TNANO.2005.846936, 2004 Silicon Nanoelectronics Workshop
-
M. Kozicki, M. Park, and M. Mitkova, "Nanoscale memory elements based on solid-state electrolytes," IEEE Trans. Nanotechnol., vol. 4, no. 3, pp. 331-338, May 2005. (Pubitemid 40794460)
-
(2005)
IEEE Transactions on Nanotechnology
, vol.4
, Issue.3
, pp. 331-338
-
-
Kozicki, M.N.1
Park, M.2
Mitkova, M.3
-
10
-
-
79956159040
-
Electrochemical metallization memories: Fundamentals, applications, prospects
-
I. Valov, R. Waser, J. Jameson, and M. Kozicki, "Electrochemical metallization memories: Fundamentals, applications, prospects," Nanotechnology, vol. 22, no. 25, pp. 1-22, 2011.
-
(2011)
Nanotechnology
, vol.22
, Issue.25
, pp. 1-22
-
-
Valov, I.1
Waser, R.2
Jameson, J.3
Kozicki, M.4
-
11
-
-
79951815188
-
High performance ultra-low energy RRAM with good retention and endurance
-
C. Cheng, C. Tsai, A. Chin, and F. Yeh, "High performance ultra-low energy RRAM with good retention and endurance," in Proc. IEEE Int. Electron Devices Meet., 2010, pp. 19.4.1-19.4.4.
-
(2010)
Proc. IEEE Int. Electron Devices Meet
, pp. 1941-1944
-
-
Cheng, C.1
Tsai, C.2
Chin, A.3
Yeh, F.4
-
12
-
-
84863020678
-
10 × 10 nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation
-
B. Govoreanu, G. Kar, Y. Chen, V. Paraschiv, S. Kubicek, A. Fantini, I. P. Radu, L. Goux, S. Clima, R. Degraeve, N. Jossart, O. Richard, T. Vandeweyer, K. Seo, P. Hendrickx, G. Pourtois, H. Bender, L. Altimime, D. Wouters, J. Kittl, and M. Jurczak, "10 × 10 nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation," in Proc. IEEE Int. Electron Devices Meet., 2011, pp. 31.6.1-31.6.4.
-
(2011)
Proc. IEEE Int. Electron Devices Meet
, pp. 3161-3164
-
-
Govoreanu, B.1
Kar, G.2
Chen, Y.3
Paraschiv, V.4
Kubicek, S.5
Fantini, A.6
Radu, I.P.7
Goux, L.8
Clima, S.9
Degraeve, R.10
Jossart, N.11
Richard, O.12
Vandeweyer, T.13
Seo, K.14
Hendrickx, P.15
Pourtois, G.16
Bender, H.17
Altimime, L.18
Wouters, D.19
Kittl, J.20
Jurczak, M.21
more..
-
13
-
-
79960642086
-
A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O5- x/TaO2-x bilayer structures
-
M. Lee, C. Lee, D. Lee, S. Lee, M. Chang, J. Hur, Y. Kim, C. Kim, D. Seo, S. Seo, U. Chung, I. Yoo, and K. Kim, "A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O5- x/TaO2-x bilayer structures," Nat. Mater., vol. 10, no. 8, pp. 625-630, 2011.
-
(2011)
Nat. Mater
, vol.10
, Issue.8
, pp. 625-630
-
-
Lee, M.1
Lee, C.2
Lee, D.3
Lee, S.4
Chang, M.5
Hur, J.6
Kim, Y.7
Kim, C.8
Seo, D.9
Seo, S.10
Chung, U.11
Yoo, I.12
Kim, K.13
-
14
-
-
0015127532
-
Memristor - The missing circuit element
-
Sep
-
L. Chua, "Memristor-the missing circuit element," IEEE Trans. Circuit Theory, vol. CT-18, no. 5, pp. 507-519, Sep. 1971.
-
(1971)
IEEE Trans. Circuit Theory, Vol. CT-18
, Issue.5
, pp. 507-519
-
-
Chua, L.1
-
15
-
-
0016918810
-
Memristive devices and systems
-
Feb
-
L. Chua and S. Kang, "Memristive devices and systems," Proc. IEEE, vol. 64, no. 2, pp. 209-223, Feb. 1976.
-
(1976)
Proc. IEEE
, vol.64
, Issue.2
, pp. 209-223
-
-
Chua, L.1
Kang, S.2
-
16
-
-
79952921400
-
Two-terminal resistive switches (memristors) for memory and logic applications
-
W. Lu, K.-H. Kim, T. Chang, and S. Gaba, "Two-terminal resistive switches (memristors) for memory and logic applications," in Proc. Asia South Pacif. Design Autom. Conf., 2011, pp. 217-223.
-
(2011)
Proc. Asia South Pacif. Design Autom. Conf
, pp. 217-223
-
-
Lu, W.1
Kim, K.-H.2
Chang, T.3
Gaba, S.4
-
17
-
-
76449096940
-
Nanoscale resistive memory with intrinsic diode characteristics and long endurance
-
K. Kim, S. Jo, S. Gaba, and W. Lu, "Nanoscale resistive memory with intrinsic diode characteristics and long endurance," Appl. Phys. Lett., vol. 96, no. 5, pp. 053 106.1-053 106.3, 2010.
-
(2010)
Appl. Phys. Lett
, vol.96
, Issue.5
, pp. 0531061-0531063
-
-
Kim, K.1
Jo, S.2
Gaba, S.3
Lu, W.4
-
18
-
-
40449092679
-
CMOS compatible nanoscale nonvolatile resistance switching memory
-
DOI 10.1021/nl073225h
-
S. Jo and W. Lu, "CMOS compatible nanoscale nonvolatile resistance switching memory," Nano Lett., vol. 8, no. 2, pp. 392-397, 2008. (Pubitemid 351345988)
-
(2008)
Nano Letters
, vol.8
, Issue.2
, pp. 392-397
-
-
Jo, S.H.1
Lu, W.2
-
19
-
-
84855772398
-
A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications
-
K. Kim, S. Gaba, D. Wheeler, J. Cruz-Albrecht, T. Hussain, and N. Srinivasa, W. Lu, "A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications," Nano Lett., vol. 12, no. 1, 2012.
-
(2012)
Nano Lett
, vol.12
, Issue.1
-
-
Kim, K.1
Gaba, S.2
Wheeler, D.3
Cruz-Albrecht, J.4
Hussain, T.5
Srinivasa, N.6
Lu, W.7
-
20
-
-
61649104641
-
Programmable resistance switching in nanoscale two-terminal devices
-
S. Jo, K. Kim, and W. Lu, "Programmable resistance switching in nanoscale two-terminal devices," Nano Lett., vol. 9, no. 1, pp. 496-500, 2008.
-
(2008)
Nano Lett
, vol.9
, Issue.1
, pp. 496-500
-
-
Jo, S.1
Kim, K.2
Lu, W.3
-
21
-
-
66649107847
-
Coupled ionic and electronic transport model of thin-film semiconductor memristive behavior
-
D. Strukov, J. Borghetti, and R. Williams, "Coupled ionic and electronic transport model of thin-film semiconductor memristive behavior," Small, vol. 5, no. 9, pp. 1058-1063, 2009.
-
(2009)
Small
, vol.5
, Issue.9
, pp. 1058-1063
-
-
Strukov, D.1
Borghetti, J.2
Williams, R.3
-
22
-
-
79959349788
-
Molecular dynamics simulations of oxide memristors: Thermal effects
-
S. Savelev, A. Alexandrov, A. Bratkovsky, and R. Williams, "Molecular dynamics simulations of oxide memristors: Thermal effects," Appl. Phys. A, Mater. Sci. Process., vol. 102, no. 4, pp. 891-895, 2011.
-
(2011)
Appl. Phys. A, Mater. Sci. Process
, vol.102
, Issue.4
, pp. 891-895
-
-
Savelev, S.1
Alexandrov, A.2
Bratkovsky, A.3
Williams, R.4
-
24
-
-
84859206837
-
Observation of conducting filament growth in nanoscale resistive memories
-
Y. Yang, P. Gao, S. Gaba, T. Chang, X. Pan, and W. Lu, "Observation of conducting filament growth in nanoscale resistive memories," Nat. Commun., vol. 3, no. 732, pp. 1-8, 2012.
-
(2012)
Nat. Commun
, vol.3
, Issue.732
, pp. 1-8
-
-
Yang, Y.1
Gao, P.2
Gaba, S.3
Chang, T.4
Pan, X.5
Lu, W.6
-
25
-
-
76649133422
-
Atomic structure of conducting nanofilaments in TiO2 resistive switching memory
-
D. Kwon, K. Kim, J. Jang, J. Jeon, M. Lee, G. Kim, X. Li, G. Park, B. Lee, S. Han, M. Kim, and C. Hwang, "Atomic structure of conducting nanofilaments in TiO2 resistive switching memory," Nat. Nanotechnol., vol. 5, no. 2, pp. 148-153, 2010.
-
(2010)
Nat. Nanotechnol
, vol.5
, Issue.2
, pp. 148-153
-
-
Kwon, D.1
Kim, K.2
Jang, J.3
Jeon, J.4
Lee, M.5
Kim, G.6
Li, X.7
Park, G.8
Lee, B.9
Han, S.10
Kim, M.11
Hwang, C.12
-
26
-
-
77955732575
-
Direct identification of the conducting channels in a functioning memristive device
-
J. Strachan, M. Pickett, J. Yang, S. Aloni, A. D. Kilcoyne, G. Medeiros- Ribeiro, and R. Williams, "Direct identification of the conducting channels in a functioning memristive device," Adv. Mater., vol. 22, no. 32, pp. 3573-3577, 2010.
-
(2010)
Adv. Mater
, vol.22
, Issue.32
, pp. 3573-3577
-
-
Strachan, J.1
Pickett, M.2
Yang, J.3
Aloni, S.4
Kilcoyne, A.D.5
Medeiros- Ribeiro, G.6
Williams, R.7
-
27
-
-
80052597371
-
Device and SPICE modeling of RRAM devices
-
P. Sheridan, K. Kim, S. Gaba, T. Chang, L. Chen, and W. Lu, "Device and SPICE modeling of RRAM devices," Nanoscale, vol. 3, no. 9, pp. 3833-3840, 2011.
-
(2011)
Nanoscale
, vol.3
, Issue.9
, pp. 3833-3840
-
-
Sheridan, P.1
Kim, K.2
Gaba, S.3
Chang, T.4
Chen, L.5
Lu, W.6
-
28
-
-
78349261547
-
Self-adaptive write circuit for low-power and variation- tolerantmemristors
-
Nov
-
K. Jo, C. Jung, K. Min, and S. Kang, "Self-adaptive write circuit for low-power and variation-tolerantmemristors," IEEE Trans. Nanotechnol., vol. 9, no. 6, pp. 675-678, Nov. 2010.
-
(2010)
IEEE Trans. Nanotechnol
, vol.9
, Issue.6
, pp. 675-678
-
-
Jo, K.1
Jung, C.2
Min, K.3
Kang, S.4
-
29
-
-
31944451658
-
Resistor-logic demultiplexers for nanoelectronics based on constant-weight codes
-
DOI 10.1088/0957-4484/17/4/035, PII S0957448406089537
-
P. Kuekes, W. Robinett, R. Roth, G. Seroussi, G. Snider, and R. Williams, "Resistor-logic demultiplexers for nanoelectronics based on constantweight codes," Nanotechnology, vol. 17, no. 4, pp. 1052-1061, 2006. (Pubitemid 43190503)
-
(2006)
Nanotechnology
, vol.17
, Issue.4
, pp. 1052-1061
-
-
Kuekes, P.J.1
Robinett, W.2
Roth, R.M.3
Seroussi, G.4
Snider, G.S.5
Williams, R.S.6
-
30
-
-
23444432868
-
Improved voltage margins using linear error-correcting codes in resistor-logic demultiplexers for nanoelectronics
-
DOI 10.1088/0957-4484/16/9/001, PII S0957448405974795
-
P. Kuekes, W. Robinett, and R. Williams, "Improved voltage margins using linear error-correcting codes in resistor-logic demultiplexers for nanoelectronics," Nanotechnology, vol. 16, no. 9, pp. 1419-1432, 2005. (Pubitemid 41107788)
-
(2005)
Nanotechnology
, vol.16
, Issue.9
, pp. 1419-1432
-
-
Kuekes, P.J.1
Robinett, W.2
Williams, R.S.3
-
32
-
-
85041688210
-
Stochastic computing elements and systems
-
W. Poppelbaum, C. Afuso, and J. Esch, "Stochastic computing elements and systems," in Proc. Fall Joint Comput. Conf., 1967, pp. 635-644.
-
(1967)
Proc. Fall Joint Comput. Conf
, pp. 635-644
-
-
Poppelbaum, W.1
Afuso, C.2
Esch, J.3
-
33
-
-
84924107520
-
Random-pulse machines
-
Jun
-
S. Ribeiro, "Random-pulse machines," IEEE Trans. Electron. Comput., vol. EC-16, no. 3, pp. 261-276, Jun. 1967.
-
(1967)
IEEE Trans. Electron. Comput
, vol.EC-16
, Issue.3
, pp. 261-276
-
-
Ribeiro, S.1
-
34
-
-
70350584618
-
A reconfigurable stochastic architecture for highly reliable computing
-
X. Li, W. Qian, M. Riedel, K. Bazargan, and D. Lilja, "A reconfigurable stochastic architecture for highly reliable computing," in Proc. Great Lakes Symp. VLSI, 2009, pp. 315-320.
-
(2009)
Proc. Great Lakes Symp. VLSI
, pp. 315-320
-
-
Li, X.1
Qian, W.2
Riedel, M.3
Bazargan, K.4
Lilja, D.5
-
35
-
-
78649938802
-
An architecture for fault-tolerant computation with stochastic logic
-
Jan
-
W. Qian, X. Li, M. Riedel, K. Bazargan, and D. Lilja, "An architecture for fault-tolerant computation with stochastic logic," IEEE Trans. Comput., vol. 60, no. 1, pp. 93-105, Jan. 2011.
-
(2011)
IEEE Trans. Comput
, vol.60
, Issue.1
, pp. 93-105
-
-
Qian, W.1
Li, X.2
Riedel, M.3
Bazargan, K.4
Lilja, D.5
-
36
-
-
51549098018
-
The synthesis of robust polynomial arithmetic with stochastic logic
-
W. Qian and M. Riedel, "The synthesis of robust polynomial arithmetic with stochastic logic," in Proc. Design Autom. Conf., 2008, pp. 648-653.
-
(2008)
Proc. Design Autom. Conf
, pp. 648-653
-
-
Qian, W.1
Riedel, M.2
-
37
-
-
84891863627
-
High-speed matrix inversion by stochastic computer
-
P. Mars and H. Mclean, "High-speed matrix inversion by stochastic computer," Electron. Lett., vol. 12, no. 18, pp. 457-459, 1976.
-
(1976)
Electron. Lett
, vol.12
, Issue.18
, pp. 457-459
-
-
Mars, P.1
McLean, H.2
-
38
-
-
4243791546
-
Stochastic pulse coded arithmetic
-
S. Toral, J. Quero, and L. Franquelo, "Stochastic pulse coded arithmetic," in Proc. IEEE Int. Symp. Circuits Syst., 2000, vol. 1, pp. 599-602.
-
(2000)
Proc. IEEE Int. Symp. Circuits Syst
, vol.1
, pp. 599-602
-
-
Toral, S.1
Quero, J.2
Franquelo, L.3
-
39
-
-
0034856257
-
Impulses and stochastic arithmetic for signal processing
-
J. Keane and L. Atlas, "Impulses and stochastic arithmetic for signal processing," in Proc. IEEE Int. Conf. Acoust., Speech, Signal Process., 2001, vol. 2, pp. 1257-1260. (Pubitemid 32839152)
-
(2001)
ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
, vol.2
, pp. 1257-1260
-
-
Keane, J.F.1
Atlas, L.E.2
-
40
-
-
84943249243
-
Stochastic arithmetic implementations of neural networks with in situ learning
-
J. Dickson, R. McLeod, and H. Card, "Stochastic arithmetic implementations of neural networks with in situ learning," in Proc. IEEE Int. Conf. Neural Netw., 1993, pp. 711-716.
-
(1993)
Proc. IEEE Int. Conf. Neural Netw
, pp. 711-716
-
-
Dickson, J.1
McLeod, R.2
Card, H.3
-
41
-
-
0029375830
-
Architecture and statistical model of a pulsemode digital multilayer neural network
-
Sep
-
Y. Kim and M. Shanblatt, "Architecture and statistical model of a pulsemode digital multilayer neural network," IEEE Trans. Neural Netw., vol. 6, no. 5, pp. 1109-1118, Sep. 1995.
-
(1995)
IEEE Trans. Neural Netw
, vol.6
, Issue.5
, pp. 1109-1118
-
-
Kim, Y.1
Shanblatt, M.2
-
42
-
-
0035440487
-
Stochastic neural computation I: Computational elements
-
DOI 10.1109/12.954505
-
B. Brown and H. Card, "Stochastic neural computation-Part I: Computational elements," IEEE Trans. Comput., vol. 50, no. 9, pp. 891-905, Sep. 2001. (Pubitemid 32981667)
-
(2001)
IEEE Transactions on Computers
, vol.50
, Issue.9
, pp. 891-905
-
-
Brown, B.D.1
Card, H.C.2
-
43
-
-
0038757578
-
A 96×64 intelligent digital pixel array with extended binary stochastic arithmetic
-
T. Hammadou, M. Nilson, A. Bermak, and P. Ogunbona, "A 96×64 intelligent digital pixel array with extended binary stochastic arithmetic," in Proc. Int. Symp. Circuits Syst., 2003, vol. 4, pp. IV-772-IV-775.
-
(2003)
Proc. Int. Symp. Circuits Syst
, vol.4
-
-
Hammadou, T.1
Nilson, M.2
Bermak, A.3
Ogunbona, P.4
-
44
-
-
0037421811
-
Iterative decoding using stochastic computation
-
V. Gaudet and A. Rapley, "Iterative decoding using stochastic computation," Electron. Lett., vol. 39, no. 3, pp. 299-301, 2003.
-
(2003)
Electron. Lett
, vol.39
, Issue.3
, pp. 299-301
-
-
Gaudet, V.1
Rapley, A.2
-
45
-
-
33750049936
-
Stochastic decoding of LDPC codes
-
DOI 10.1109/LCOMM.2006.060570
-
S. Sharifi Tehrani, W. Gross, and S. Mannor, "Stochastic decoding of LDPC codes," IEEE Commun. Lett., vol. 10, no. 10, pp. 716-718, Oct. 2006. (Pubitemid 44575771)
-
(2006)
IEEE Communications Letters
, vol.10
, Issue.10
, pp. 716-718
-
-
Tehrani, S.S.1
Gross, W.J.2
Mannor, S.3
-
46
-
-
84883229739
-
Stochastic memristive devices for computing and neuromorphic applications
-
S. Gaba, P. Sheridan, J. Zhou, S. Choi, and W. Lu, "Stochastic memristive devices for computing and neuromorphic applications," Nanoscale, vol. 5, pp. 5872-5878, 2013.
-
(2013)
Nanoscale
, vol.5
, pp. 5872-5878
-
-
Gaba, S.1
Sheridan, P.2
Zhou, J.3
Choi, S.4
Lu, W.5
-
47
-
-
0028427038
-
Generating binary sequences for stochastic computing
-
May
-
P. Jeavons, D. Cohen, and J. Shawe-Taylor, "Generating binary sequences for stochastic computing," IEEE Trans. Inf. Theory, vol. 40, no. 3, pp. 716-720, May 1994.
-
(1994)
IEEE Trans. Inf. Theory
, vol.40
, Issue.3
, pp. 716-720
-
-
Jeavons, P.1
Cohen, D.2
Shawe-Taylor, J.3
-
48
-
-
33744478374
-
Mapping structures for flash memories: Techniques and open problems
-
DOI 10.1109/SWSTE.2005.14, 1421068, Proceedings - IEEE International Conference on Software - Science, Technology and Engineering 2005, SwSTE '05
-
E. Gal and S. Toledo, "Mapping structures for flash memories: Techniques and open problems," in Proc. IEEE Int. Conf. Softw., Sci., Technol. Eng., 2005, pp. 83-92. (Pubitemid 43803516)
-
(2005)
Proceedings - IEEE International Conference on Software - Science, Technology and Engineering 2005, SwSTE '05
, vol.2005
, pp. 83-92
-
-
Gal, E.1
Toledo, S.2
-
51
-
-
0001457509
-
Some methods for classification and analysis of multivariate observations
-
J. MacQueen, "Some methods for classification and analysis of multivariate observations," in Proc. Berkeley Symp. Math. Statist. Probabil., 1967, vol. 1, pp. 281-297.
-
(1967)
Proc. Berkeley Symp. Math. Statist. Probabil
, vol.1
, pp. 281-297
-
-
Macqueen, J.1
|