A 96 × 64 Intelligent digital pixel array with extended binary stochastic arithmetic

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2003, Pages

  Hammadou, Tarik ^a   Nilson, Magnus ^a   Bermak, Amine ^b   Ogunbona, Philip ^a  

^a Motorola Australia   (Australia)

^b HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; IMAGE PROCESSING; PULSE TIME MODULATION; VLSI CIRCUITS;

PIXEL LEVEL PROCESSING;

IMAGE SENSORS;

EID: 0038757578     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. B.D. Brown & H.C. Card "Stochastic neural computation. II. Soft competitive learning", IEEE Trans. on Computers, vol 50, No. 9, September 2001, pp 906-920.
2. J.F. Keane & L.E. Atlas "Impulses and stochastic arithmetic for signal processing", IEEE International Conference on Acoustics, Speech, and Signal Processing, Salt Lake City, vol. 2, pp. 1257-1260, 2001
3. T. Hammadou & A. Bouzerdoum "Novel Image Enhancement Technique Using Shunting Inhibitory Cellular Neural Networks", IEEE Trans. on Consumer Electronics, vol 47, No. 4, November 2001, pp 934-940.