Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations

ACM Transactions on Reconfigurable Technology and Systems

Volumn 1, Issue 1, 2008, Pages 1-31

  Matsumoto, Yohei ^a   Hioki, Masakazu ^a   Kawanami, Takashi ^a   Koike, Hanpei ^a   Tsutsumi, Toshiyuki ^b   Nakagawa, Tadashi ^a   Sekigawa, Toshihiro ^a  

^a NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

^b MEIJI UNIVERSITY   (Japan)

Author keywords

configuration; FPGA; Reliability; timing yield; within die variation

Indexed keywords

EID: 84896862219     PISSN: 19367406     EISSN: 19367414     Source Type: Journal    
DOI: 10.1145/1331897.1331899     Document Type: Article

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