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Volumn 2778, Issue , 2003, Pages 828-838

Evaluation of testability of path delay faults for user-configured programmable devices

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS;

EID: 35248864461     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-45234-8_80     Document Type: Review
Times cited : (4)

References (16)
  • 1
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    • Delay Testing Considering Crosstalk-Induced Effects
    • Krstic, A., Liou, J.-J.: Delay Testing Considering Crosstalk-Induced Effects. In: Proc. IEEE Int. Test Conf. (2001) 558-567
    • (2001) Proc. IEEE Int. Test Conf. , pp. 558-567
    • Krstic, A.1    Liou, J.-J.2
  • 2
    • 0035684722 scopus 로고    scopus 로고
    • On-Line Testing of Transient and Crosstalk Faults Affecting Interconnections of FPGA-Implemented Systems
    • Metra, C., Pagano, A., Ricco, B.: On-Line Testing of Transient and Crosstalk Faults Affecting Interconnections of FPGA-Implemented Systems. In: Proc. IEEE Int. Test Conf. (2001) 939-947
    • (2001) Proc. IEEE Int. Test Conf. , pp. 939-947
    • Metra, C.1    Pagano, A.2    Ricco, B.3
  • 6
    • 0029700620 scopus 로고    scopus 로고
    • Built-In Self-Test of Logic Blocks in FPGAs (Finally, a Free Lunch: BIST Without Overhead!)
    • Stroud, C., Konala, S., Chen, P., Abramovici, M.: Built-In Self-Test of Logic Blocks in FPGAs (Finally, a Free Lunch: BIST Without Overhead!). In: Proc. 14th VLSI Test Symp. (1996), 387-392
    • (1996) Proc. 14th VLSI Test Symp. , pp. 387-392
    • Stroud, C.1    Konala, S.2    Chen, P.3    Abramovici, M.4
  • 8
    • 0141873646 scopus 로고    scopus 로고
    • Testing FPGA Delay Faults: It Is Much More Complicated Than It Appears
    • Ciazynski W. et al. (eds.), Pergamon - Elsevier Science
    • Krasniewski, A.: Testing FPGA Delay Faults: It Is Much More Complicated Than It Appears. In: Ciazynski W. et al. (eds.), Programmable Devices and Systems, Pergamon - Elsevier Science (2002) 281-286
    • (2002) Programmable Devices and Systems , pp. 281-286
    • Krasniewski, A.1
  • 9
    • 0029213728 scopus 로고
    • Fast Identification of Robust Dependent Path Delay Faults
    • Sparmann, U. et al.: Fast Identification of Robust Dependent Path Delay Faults. In: Proc. 32nd ACM/IEEE Design Automation Conf. (1995) 119-125
    • (1995) Proc. 32nd ACM/IEEE Design Automation Conf. , pp. 119-125
    • Sparmann, U.1
  • 10
    • 0030214852 scopus 로고    scopus 로고
    • Classification and Identification of Nonrobust Untestable Path Delay Faults
    • Cheng, K.-T., Chen, H.-C.: Classification and Identification of Nonrobust Untestable Path Delay Faults. IEEE Trans. on CAD, 8 (1996) 845-853
    • (1996) IEEE Trans. on CAD , vol.8 , pp. 845-853
    • Cheng, K.-T.1    Chen, H.-C.2
  • 11
    • 0032652488 scopus 로고    scopus 로고
    • Primitive Delay Faults: Identification, Testing, and Design for Testability
    • Krstic, A., Cheng, K.-T., Chakradhar, S.T.: Primitive Delay Faults: Identification, Testing, and Design for Testability. IEEE Trans. on CAD, 11 (1999) 669-684
    • (1999) IEEE Trans. on CAD , vol.11 , pp. 669-684
    • Krstic, A.1    Cheng, K.-T.2    Chakradhar, S.T.3
  • 12
    • 35248879245 scopus 로고    scopus 로고
    • Sensitization of Logical Paths in a Network of Arbitrary Logic Components: Theory and Application to Delay Fault Testing
    • Krasniewski, A.: Sensitization of Logical Paths in a Network of Arbitrary Logic Components: Theory and Application to Delay Fault Testing. In: Proc. IEEE Design and Diagnostics of Electronics Circuits and Systems Workshop (2003) 143-150
    • (2003) Proc. IEEE Design and Diagnostics of Electronics Circuits and Systems Workshop , pp. 143-150
    • Krasniewski, A.1
  • 13
    • 79955154748 scopus 로고    scopus 로고
    • On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-Based FPGAs
    • Glesner, M., Zipf, P., Renovell, M. (eds.), Proc. FPL 2002, Springer Verlag
    • Krasniewski, A.: On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-Based FPGAs. In: Glesner, M., Zipf, P., Renovell, M. (eds.), Proc. FPL 2002, LNCS, vol. 2438, Springer Verlag (2002) 616-626
    • (2002) LNCS , vol.2438 , pp. 616-626
    • Krasniewski, A.1
  • 16
    • 84944067501 scopus 로고    scopus 로고
    • Evaluation of the Quality of Testing Path Delay Faults under Restricted Input Assumption
    • in printing
    • Krasniewski, A.: Evaluation of the Quality of Testing Path Delay Faults Under Restricted Input Assumption. In: Proc. IEEE Int. On-Line Testing Symp. (2003) (in printing).
    • (2003) Proc. IEEE Int. On-Line Testing Symp.
    • Krasniewski, A.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.