FPGA as process monitor - An effective method to characterize poly gate CD variation and its impact on product performance and yield

IEEE Transactions on Semiconductor Manufacturing

Volumn 17, Issue 3, 2004, Pages 267-272

  Li, Xiao Yu ^a   Wang, Feng ^a   La, Tho ^a   Ling, Zhi Min ^a  

^a XILINX INC   (United States)

Author keywords

Field programmable gate array (FPGA); Poly gate critical dimension (CD); Process monitor and yield

Indexed keywords

BUILT-IN SELF TEST; FLIP FLOP CIRCUITS; POLYSILICON; RANDOM ACCESS STORAGE; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR DOPING; VECTORS;

CONFIGURABLE LOGIC BLOCKS (CLB); LINE EDGE ROUGHNESS (LER); POLY GATE CRITICAL DIMENSION; POLYSILICON GATES;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 4344561555     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2004.831934     Document Type: Conference Paper

References (5)

1. A. Yu et al., Polysilicon gate pattering, in IEDM Short Course: Sub-100 nm CMOS, Washington, DC, 1999.
2. T. Linton, M. Chandhok, B. J. Rice, and G. Schrom, "Determination of the line edge roughness specification for 34 nm devices," in Proc. Int. Electron Devices Meeting (IEDM), Dec. 2002, pp. 303-306.
3. J. Sturtevant et al., "Characterization of CD control for sub-0.18 um lithographic patterning," in Proc. SPIE, 1999, pp. 220-227.
4. M. Orshansky et al., "Intra field gate CD variability and it's impact on circuit performance," in Proc. IEDM, 2002, p. 303.
5. A. Calderone, F. Wang, and T. La, "Methods and circuits for testing a circuit fabrication process for device uniformity," U.S. Patent 6 507 942, Jan. 2003.