Placement and timing for FPGAS considering variations

Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2006, Pages 37-43

  Lin, Yan ^a   Hutton, Mike ^b   He, Lei ^a  

^a Engineering IV   (United States)

^b ALTERA CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRITICAL PATHS; FIELD PROGRAMMABLE LOGIC (FPL); IN DEPTH STUDIES; INTERNATIONAL CONFERENCES; NANOMETER TECHNOLOGIES; ON-CHIP VARIATIONS; PROCESS VARIATIONS; RE PROGRAMMABILITY; STATISTICAL ALGORITHMS; STATISTICAL PERFORMANCES; STATISTICAL TIMING ANALYSIS; TEST TIME; YIELD LOSSES;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FUZZY LOGIC; INTEGRATED CIRCUITS; NETWORKS (CIRCUITS); STATISTICAL METHODS; STATISTICS; TIME MEASUREMENT;

TIMING CIRCUITS;

EID: 46249113560     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2006.311192     Document Type: Conference Paper

References (11)

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5. A. Marquardt, V. Betz and J. Rose, "Timing-Driven Placement for FPGAs", Proc. Int'l Symp. FPGAs, Feb 2000
6. C. Visweswariah et al, "First-Order Incremental Block-based Statistical Timing Analysis", Proc. of DAC, 2004
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8. Altera Corp, "QUIP for Quartus II V5.0", available at http://www.altera.com/education/univ.
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10. H. Chang and S. Sapatnekar, "Statistical timing analysis considering spatial correlations using a single pert-like traversal", Proc. of ICCAD, 2003
11. C.E. Clark, "The greatest of a finite set of random variables", in Operation Research, Vol. 9, No.2, 1961