Yield enhancements of design-specific FPGAs

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2006, Pages 93-100

  Campregher, Nicola ^a   Cheung, Peter Y K ^a   Constantinides, George A ^a   Vasilko, Milan ^b  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

^b BOURNEMOUTH UNIVERSITY   (United Kingdom)

Author keywords

Design specific FPGA; FPGA interconnect; Interconnect faults; Interconnect utilization; Structured ASIC; Yield enhancement; Yield prediction

Indexed keywords

CONFORMAL MAPPING; COSTS; ELECTRIC CURRENT DISTRIBUTION; LOGIC DESIGN; MATHEMATICAL MODELS; PROBABILITY; SILICON WAFERS; SOFTWARE PROTOTYPING;

DESIGN-SPECIFIC FPGA; FPGA INTERCONNECT; INTERCONNECT FAULTS; INTERCONNECT UTILIZATION; YIELD ENHANCEMENT; YIELD PREDICTION;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33745856285     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1117201.1117215     Document Type: Conference Paper

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