Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 8, 2000, Pages 1186-1193

  Bowman, Keith A ^a   Tang, Xinghai ^b   Eble, John C ^c   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b MOTOROLA INC   (United States)

^c HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL METHODS; ELECTRIC LOSSES; ELECTRIC POWER SUPPLIES TO APPARATUS; LOGIC CIRCUITS; MATHEMATICAL MODELS; MOS CAPACITORS; MOSFET DEVICES; PARAMETER ESTIMATION;

CHANNEL DOPING; CMOS LOGIC CIRCUIT; CRITICAL PATH DELAY; LOWER CLOCK FREQUENCY; PARAMETER FLUCTUATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034246776     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.859508     Document Type: Article

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