Modeling within-field gate length spatial variation for process-design co-optimization

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5756, Issue , 2005, Pages 178-188

  Friedberg, Paul ^a   Cao, Yu ^a   Cain, Jason ^a   Wang, Ruth ^a   Rabaey, Jan ^a   Spanos, Costas ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Circuit performance; Gate length variation; Process control; Spatial correlation; Variability

Indexed keywords

CIRCUIT PERFORMANCE; GATE LENGTH VARIATION; SPATIAL CORRELATION; VARIABILITY;

DATA REDUCTION; LITHOGRAPHY; MATHEMATICAL MODELS; MONTE CARLO METHODS; OPTICAL CORRELATION; PROCESS CONTROL; SILICON WAFERS;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 25144483328     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.600028     Document Type: Conference Paper

References (10)

1. M. Pelgrom, A. Duinmaijer, and A. Welbers, "Matching properties of MOS transistors," IEEE Journal of Solid-State Circuits, vol. 24, no. 1, pp. 1433-1439, Oct. 1989.
2. B. E. Stine, D. S. Boning, and J. E. Chung, "Analysis and decomposition of spatial variation in integrated circuit processes and devices," IEEE Transactions on Semiconductor Manufacturing, vol. 10, no. 1, Feb. 19.
3. International Technology Roadmap for Semiconductors, 2003.
4. S. Nassif, "Design for manufacturability in DSM technologies," IEEE International Symposium on Quality Electronics Design, pp. 451-454, 2000.
5. X. Niu, N. Jakatdar, J. Bao, and C. Spanos, "Specular Spectroscopic Scatterometry," IEEE Transactions on Semiconductor Manufacturing, vol. 14, no. 2, pp. 97-111, 2001.
6. Y. Cao, et al., "Design sensitivities to variability: extrapolations and assessments in nanometer VLSI," IEEE International ASIC/SoC Conference, pp. 411-415, 2002.
7. M. Orshansky, et al., "Impact of spatial intra-chip gate length variability on the performance of high speed digital circuits," IEEE Transactions on Computer-Aided Design, vol. 21, pp. 544-553, May 2002.
8. J. Cain and C. Spanos, "Electrical linewidth metrology for systematic CD variation characterization and causal analysis," Metrology, Inspection, and Process Control for Microlithography XVII, Proceedings of SPIE vol. 5038, pp. 350-361, 2003.
9. Y. Cao, et al., "New paradigm of predictive MOSFET and interconnect modeling for early circuit design," IEEE Custom Integrated Circuits Conference, pp. 201-204, 2000.
10. J. van Schoot, et al, "CD uniformity improvement by active scanner corrections," Optical Microlithography XV, Proceedings of SPIE vol. 4691, pp. 304-312, 2002.