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Volumn , Issue , 2013, Pages

System-level thermal modeling for 3D circuits: Characterization with a 65nm memory-on-logic circuit

Author keywords

3DIC; characterization; CTM; material homogenization; temperature; thermal modeling

Indexed keywords


EID: 84893966264     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2013.6702379     Document Type: Conference Paper
Times cited : (14)

References (15)
  • 1
    • 84893911972 scopus 로고    scopus 로고
    • A 0.9 pJ/bit, 12.8 GByte/s wideIO memory interface in a 3D-IC NoC-based MPSoC
    • D. Dutoit et all., "A 0.9 pJ/bit, 12.8 GByte/s wideIO memory interface in a 3D-IC NoC-based MPSoC," VLSI Symposium, Kyoto, Japan, June 2013.
    • VLSI Symposium, Kyoto, Japan, June 2013
    • Dutoit, D.1
  • 2
    • 84893910619 scopus 로고    scopus 로고
    • DOCEA Power, Inc. www.doceapower.com
  • 14
    • 84866864678 scopus 로고    scopus 로고
    • Electrical, thermal and mechanical impact of 3D TSV and 3D stacking technology on advanced CMOS devices - Technology directions
    • E. Beyne, "Electrical, thermal and mechanical impact of 3D TSV and 3D stacking technology on advanced CMOS devices - Technology directions," in 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International, 2012, pp. 1-6.
    • (2012) 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International , pp. 1-6
    • Beyne, E.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.