A simple and approximate analytical model for the estimation of the thermal resistances in 3D stacks of integrated circuits

18th International Workshop on Thermal Investigation of ICs and Systems, THERMINIC 2012

Volumn , Issue , 2012, Pages 141-146

  De Crécy, François ^a  

^a CEA GRENOBLE   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ADJUSTABLE COEFFICIENT; FEM SIMULATIONS; HOT SPOT; LATERAL SPREADING; MATERIAL PROPERTY; STEADY-STATE CONDITION; SYSTEM ARCHITECTS; Z-DIRECTIONS;

ANALYTICAL MODELS; FINITE ELEMENT METHOD; HEAT RESISTANCE; MODELS; SILICA; THREE DIMENSIONAL; THREE DIMENSIONAL COMPUTER GRAPHICS;

THERMAL CONDUCTIVITY;

EID: 84872867578     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. S.Im and K. Banerjee, Full chip thermal analysis of planar (2D) and vertically integrated (3D) high performance ICs, Tech. Dig. IEDM, 2000, pp 727-730
2. K. Banerjee, M. Pedram and A. Ajami, Analysis and optimization of thermal issues in high-performance VLSI, ACM/SIGDA International Symposium on Physical Design (IPSD), pp 230-237, April 2001
3. K. Matsumoto, S. Ibaraki, K. Sakuma, K. Sueoka, H. Kikuchi, Y. Orii and F. Yamada, Thermal Resistance Evaluation of a Three-dimensional (3D) Chip Stack, Electronics Packaging Technology Conference (EPTC) pp614-619, 2010
4. T.J. Santner, B.J. Williams, W.I. Notz, 2003, The Design and Analysis of Computer Experiments, 2003, Springer