Numerical and experimental characterization of the thermal behavior of a packaged DRAM-on-logic stack

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2012, Pages 1081-1088

  Oprins, H ^a   Cherman, V O ^a   Vandevelde, B ^a   Van Der Plas, G ^a   Marchal, P ^a   Beyne, E ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

3D TECHNOLOGY; COOLING CONFIGURATION; DIE STACK; EFFECTIVE THERMAL CONDUCTIVITY; EXPERIMENTAL CHARACTERIZATION; FINITE ELEMENT; HIGH-POWER; HOT SPOT; INTEGRATED HEATER; LOGIC CHIPS; LOW POWER; MICRO-BUMPS; SYSTEM INTEGRATION; TEMPERATURE PROFILES; THERMAL BEHAVIORS; THERMAL IMPACTS; THERMAL MODEL; UNDERFILLS;

CHARACTERIZATION; TECHNOLOGY; TEMPERATURE CONTROL; THREE DIMENSIONAL COMPUTER GRAPHICS;

DIES;

EID: 84866859437     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2012.6248970     Document Type: Conference Paper

References (22)

1. Garrou, Ph., "Handbook of 3D-Integration: Technology and Applications of 3D Integrated Circuits", Wiley-VCH (Weinheim, 2008).
2. Chanchani, R. "3D Integration Technologies - An Overview", in Materials for Advanced Packaging edited by D. Lu, C.P. Wong, Springer (2009), pp. 1-50.
3. Beyne, E. "Through-Silicon via Technology for 3D IC" in Ultra-thin Chip Technology and Applications, edited by J.N. Burghartz, Springer (2011).
4. Marchal, P. et al., "3D technology roadmap and status", Proc. IITC 2011, pp. 1-3.
5. Gu, S. et al., "Stackable memory of 3D chip integration for mobile applications", Proc. IEDM 2008, pp 1-4.
6. Brunschwiler, T.; Michel, B. ; "Thermal Management of Vertically Integrated Packages," in Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits, edited by P. Garrou, C. Bower and P. Ramm. Wiley-VCH Verlag GmbH (Weinheim, 2008) Vol. 2, Part IV, pp. 635-649.
7. Agonafer, D. et al., "Thermo-Mechanical Challenges in Stacked Packaging", Heat Transfer Engineering, Vol. 29 No. 2 (2008), pp. 134-148.
8. Van der Plas, G. et al., "Design issues and considerations for low-cost 3D TSV IC technology", IEEE Journal of Solid-State Circuits, Vol. 46 No. 1 (2010), pp. 293-307.
9. Venkatadri, V.; Sammakia, B.; Srihari,K.; Santos, D.; "A Review of Recent Advances in Thermal Management in Three Dimensional Chip Stacks in Electronic Systems", J. Electron. Packag. Volume 133 No. 4 (2011), p. 041011 (15 pages).
10. Dewan-Sandur, B.P.; Kaisare, A.; Agonafer, De.; Agonafer, Da.; Amon, C.; Pekin, S.; Dishongh, T.; , "Thermal management of die stacking architecture that includes memory and logic processor," Proceedings. 56th Electronic Components and Technology Conference, 2006.
11. Melamed, S.; Thorolfsson, T.; Srinivasan, A.; Cheng, E.; Franzon, P.; Davis, W.R.; , "Investigation of tier-swapping to improve the thermal profile of memory-onlogic 3DICs," 16th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC), Barcelona, Spain, 6-8 Oct. 2010.
12. Oprins, H.; Srinivasan, A.; Cupak, M.; Cherman, V.; Torregiani, C.; Stucchi, M.; Vandevelde, B.; Van der Plas, G.; Marchal, P. and Cheng, E., "Fine grain thermal modelling and experimental validation of 3D-ICs", Microelectronics Journal, Vol. 42 No. 4 (2011, pp. 572-578.
13. Jain, A.; Jones, R.E.; Chatterjee, R.; Pozder, S.; , "Analytical and Numerical Modeling of the Thermal Performance of Three-Dimensional Integrated Circuits," IEEE Transactions on Components and Packaging Technologies, vol.33, no.1 (2010), pp.56-63.
14. La Manna, A.; Rebibis, K.J.; Gerets, C.; Beyne, E.; "Use of Wafer Applied Underfill for 3D Stacking", IMAPS 44th International Symposium on Microelectronics, Long Beach CA, US, 2011.
15. "Standard Test Method for Thermal Transmission Properties of Thermally Conductive Electrical Insulation Materials". ASTM Standard D-5470-06, Copyright ASTM International, Conshohocken, PA, 2007.
16. th Semiconductor Thermal Measurement and Management Symposium), 2009, pp. 321 - 328.
17. Matsumoto, K. et al.;, "Experimental Thermal Resistance Evaluation of a Three-Dimensional (3D) Chip Stack, Including the Transient Measurements", 28th Semiconductor Thermal Measurement, Modeling & Management Symposium (SEMI-THERM), San Jose, CA USA, Mar 18-22 , 2012.
18. Colgan, E. et al., "Measurement of Microbump Thermal Resistance in 3D Chip Stacks", 28th Semiconductor Thermal Measurement, Modeling & Management Symposium (SEMI-THERM), San Jose, CA USA, Mar 18-22 , 2012.
19. Oprins, H. et al., "Transient analysis based thermal characterization of die-die interfaces in 3D-ICs", Thirteenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), San Diego, CA USA, May 31- June 1, 2012.
20. Oprins, H. et al., "Characterization of the Thermal Impact of Cu-Cu bonds achieved using TSVs on hot spot dissipation in 3D stacked ICs", Proceedings 61th Electronic Components and Technology Conference May 30- June 1, 2011, pp. 861-868.
21. Milojevic, D.; Oprins, H.; Ryckaert, J.; Marchal, P.; Van der Plas, G.; , "DRAM-on-logic Stack - Calibrated thermal and mechanical models integrated into PathFinding flow", IEEE Custom Integrated Circuits Conference (CICC), 2011.
22. Milojevic, D.; Varadarajan, R.; Seynhaeve, D.; Marchal, P.; "PathFinding and TechTuning" in Three Dimensional System Integration, Springer (2011), pp. 137 - 186.