Fine grain thermal modeling and experimental validation of 3D-ICs

Microelectronics Journal

Volumn 42, Issue 4, 2011, Pages 572-578

  Oprins, H ^a   Srinivasan, A ^b   Cupak, M ^a   Cherman, V ^a   Torregiani, C ^a   Stucchi, M ^a   Van Der Plas, G ^a   Marchal, P ^a   Vandevelde, B ^a   Cheng, E ^b  

^a IMEC   (Belgium)

^b Gradient Design Automation Inc   (United States)

Author keywords

3D stacked ICs; Design layout; Experimental validation; Thermal aware design; Thermal modeling; Thermal test chip

Indexed keywords

3D STACKED ICS; DESIGN LAYOUT; EXPERIMENTAL VALIDATIONS; THERMAL AWARE DESIGN; THERMAL MODELING; THERMAL TEST CHIP;

AUTOMOBILE ELECTRONIC EQUIPMENT; DIES; ELECTRONICS PACKAGING; THERMOANALYSIS; THREE DIMENSIONAL;

STRUCTURAL DESIGN;

EID: 79953307231     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2010.08.006     Document Type: Article

References (14)

1. The International Technology Roadmap for Semiconductors (ITRS), 2008 edition, URL: 〈 http://www.itrs.net/Links/2008ITRS/Home2008.htm 〉.
2. E. Beyne, The rise of the 3rd dimension for system integration, in: Proceedings of the IEEE International Interconnect Technology Conference, 2006, pp. 15.
3. M. Rencz, Thermal issues in stacked die packages, 21st IEEE Semi-therm Symposium, March 2005, pp. 307312. (Pubitemid 41696293)
4. FireBolt (nanoscale full-chip thermal simulator), Gradient Design Automation, Inc., 〈http://www.gradient-da.com/〉.
5. M. Turowski, S. Dooley, A. Raman, M. Casto, Multiscale 3D thermal analysis of analog ICs: from full-chip to device level, in: Proceedings of the 14th International Workshop on Thermal Inveatigation of ICs and Systems, 2008, pp. 6469.
6. M. Rencz, V. Székely, Structure function evaluation of stacked dies, in: Proceedings of the XXth Semi-therm Symposium, March 911, San Jose, CA, USA, 2004, pp. 5055.
7. Enrico A. Garcia, Chia-Pin Chiu: Compact modeling approaches to multiple die stacked chip scale packages, in: 19th IEEE Semi-therm Symposium, 2003, pp. 160167.
8. Li Zhang, Noella Howard, Vijaylaxmi Gumaste, Amindya Poddar, Luu Nguyen, Thermal characterization of stacked-die packages, in: 20th IEEE Semi-therm Symposium, 2004, pp. 5563.
9. R. Gillon, P. Joris, H. Oprins, B. Vandevelde, A.Srinivasan, R. Chandra, Practical chip-centric electro-thermal simulations, in: Proceedings of THERMINIC, Rome, Italy, 2426 September 2008, pp. 220223.
10. E.R. Eckert, and D. Eckert Analysis of Heat and Mass Transfer, Eq. (114) 1986 CRC Press p. 11
11. S. Melamed, T. Thorolfsson, A. Srinivasan, E. Cheng, P. Franzon, R. Davis, Junction-level thermal extraction and simulation of 3DICs, in: IEEE International Conference on 3D System Integration (3D IC), September 2009.
12. B. Swinnen et al., 3D integration by CuCu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias, in: International Electron Devices Meeting, 14, December 2006.
13. H. Oprins, V. Cherman, C. Torregiani, M. Stucchi, B. Vandevelde, E. Beyne, Thermal test vehicle for the validation of thermal modelling of hot spot dissipation in 3D stacked ICs, ESTC2010, September 2010.
14. C. Torregiani, H. Oprins, B. Vandevelde, E. Beyne, I. De Wolf, Compact thermal modeling of hot spots in advanced 3D-stacked structures, in: Proceedings of the EPTC 2009, pp. 131136.