Optimizations enabled by a decoupled front-end architecture

IEEE Transactions on Computers

Volumn 50, Issue 4, 2001, Pages 338-355

  Reinman, Glenn ^b   Calder, Brad ^a,b   Austin, Todd ^a,c  

^a IEEE

^b UNIVERSITY OF CALIFORNIA   (United States)

^c UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Branch prediction; Decoupled architectures; Fetch architectures; Instruction prefetching

Indexed keywords

C (PROGRAMMING LANGUAGE); CACHE MEMORY; COMPUTER SIMULATION; OPTIMIZATION; PIPELINE PROCESSING SYSTEMS; PROGRAM COMPILERS;

BRANCH PREDICTION; DECOUPLED FRONT END ARCHITECTURE; FETCH TARGET QUEUE; INSTRUCTION PREFETCHING;

PARALLEL PROCESSING SYSTEMS;

EID: 0035308287     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.919279     Document Type: Article

References (43)