Code layout optimizations for transaction processing workloads

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn , Issue , 2001, Pages 155-164

  Ramirez, Alex ^a   Barroso, Luiz André ^b   Gharachorloo, Kourosh ^b   Cohn, Robert ^b   Larriba Pey, Josep ^a   Lowney, P Geoffrey ^b   Valero, Mateo ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CODES (SYMBOLS); COMPUTER SIMULATION; DATA HANDLING; DATABASE SYSTEMS; MULTIPROCESSING SYSTEMS; ONLINE SYSTEMS; OPTIMIZATION; SERVERS; WORLD WIDE WEB;

ALPHA MULTIPROCESSORS; MISS RATES; ONLINE TRANSACTION PROCESSING; WEB SERVERS;

PROGRAM COMPILERS;

EID: 0034838875     PISSN: 08847495     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCA.2001.937444     Document Type: Article

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