Impact of back gate biasing schemes on energy and robustness of ULV logic in 28nm UTBB FDSOI technology

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2013, Pages 255-260

  De Streel, Guerric ^a   Bol, David ^a  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

28nm; back gate biasing; CMOS FDSOI; die yield; robustness; subthreshold logic; ultra low power; ultra low voltage

Indexed keywords

28NM; BACK-GATE BIASING; SUBTHRESHOLD LOGIC; ULTRA-LOW POWER; ULTRA-LOW-VOLTAGE;

LOW POWER ELECTRONICS; OPTIMIZATION; ROBUSTNESS (CONTROL SYSTEMS);

DESIGN;

EID: 84889583195     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISLPED.2013.6629305     Document Type: Conference Paper

References (18)

1. A. Wang, A. P. Chandrakasan, and S. V. Kosonocky, "Optimal supply and threshold scaling for subthreshold CMOS circuits", in Proc. IEEE Annu. Symp. VLSI, 2002, pp. 5-9.
2. B. H. Calhoun, A. Wang, and A. Chandrakasan, "Device Sizing for minimum energy operation for subthreshold circuits", in Proc. IEEE Int. Symp. Low Power Electronics and Design (ISLPED), 2004, pp. 90-95.
3. D. Bol, "Robust and energy-efficient ultra-low-voltage circuit design under timing constraints in 65/45nm CMOS", in Journal of Low-Power Electronics and Applications, 2011, pp. 1-19.
4. J. Kwong and A. Chandrakasan, "Variation-driven device sizing for minimum energy sub-threshold circuits", in Proc. IEEE Int. Symp. Low Power Electronics and Design (ISLPED), 2006, pp. 8-13.
5. D. Bol et al., "Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits", in Proc. IEEE Int. Symp. Low Power Electronics and Design (ISLPED), 2009, pp. 21-26.
6. Y. Pu et al., "Vt balancing and device sizing toward high yield of sub-threshold static logic gates", in Proc. IEEE Int. Symp. Low Power Electronics and Design (ISLPED), 2007, pp. 355-358.
7. M. E. Hwang et al., "ABRM: adaptivefi-ratio modulation for processtolerant ultradynamic voltage scaling", in IEEE Trans. VLSI Syst., 2010, pp. 281-290.
8. M. H. Na, "The effective drive current in CMOS inverters", in International Electron Devices Meeting (IEDM), 2002, pp. 121-124.
9. B.H. Calhoun, A. Wang, A. Chandrakasan, "Modeling and sizing for minimum energy operation in subthreshold circuits", in IEEE Journal of Solid-State Circuits, 2005, pp. 1778-1786.
10. G. Ono, M. Miyazaki, "Threshold-voltage balance for minimum supply operation", in IEEE Journal of Solid-State Circuits, 2003, pp. 830-833.
11. O. Thomas et al., "32nm and beyond multi-VT Ultra-bhin body and BOX FDSOI: from device to circuit", in Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS), 2010, pp. 1703-1706.
12. Y. Pu, J. P. de Gyvez, H. Corporaal, H. Yajun, "Statistical noise margin estimation for sub-threshold combinational circuits", in Asia and South Pacific Design Automation Conference (ASPDAC), 2008, pp. 176-179.
13. D. Bol, D. Flandre, J.-D. Legat, "Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold LogicMitigation at Technology and Circuit Levels", in ACM Transactions on Design Automation of Electronic Systems (TODAES), 2010.
14. V. Kilchytska et al., "On the UTBB SOI MOSFET performance improvement in quasi-double-gate regime", in Proc. of the European Solid-State Device Research Conference (ESSDERC), 2012, pp. 246-249.
15. P. Flatresse, "Product Vision on Planar Fully Depleted Technology FD28nm for Mobile Applications", in IEEE Int. SOI Conf., 2012.
16. O. Weber et al., "High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding", in International Electron Devices Meeting (IEDM), 2008, pp. 1-4.
17. F. Abouzeid et al., "28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0V, 10MHz/700MHz, 252bits frame error-decoder ", in Proceedings of the ESSCIRC, 2012, pp. 153-156.
18. D. Bol, R. Ambroise, D. Flandre and J.-D. Legat, Sub-45nm fullydepleted SOI CMOS subthreshold logic for ultra-low-power applications, in Proc. IEEE International SOI Conference, 2 p., 2008