On the UTBB SOI MOSFET performance improvement in quasi-double-gate regime

European Solid-State Device Research Conference

Volumn , Issue , 2012, Pages 246-249

  Kilchytska, V ^a   Flandre, D ^a   Andrieu, F ^b  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

^b CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG APPLICATIONS; CIRCUIT IMPLEMENTATION; DIGITAL APPLICATIONS; GROUND PLANES; HIGH-PRECISION; OFF-STATE CURRENT; ON-CURRENTS; PERFORMANCE ENHANCEMENTS; SOI-MOSFETS; THRESHOLD VOLTAGE TUNING;

MOSFET DEVICES;

EID: 84870611983     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2012.6343379     Document Type: Conference Paper

References (8)

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2. F. Andrieu, et al. , "Low leakage and low variability ulita-thin body and buried oxide (UT2B) SOI technology for 20nm low power CMOS and beyond", VLSI Symp. 2010, pp. 57-58.
3. F. Balestra, et al. , "Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance", IEEE Electron Dev. Lett. , vol. EDL-8, no. 9, 1987, pp. 410-412.
4. T. Ernst et al. , "Ultimately thin double-gate SOI MOSFETs," IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 830-838, 2003.
5. V. Kilchytska, et al. "Investigation of charge control-related perfor-mances in double-gate SOI MOSFETs," 11th Int. SOI symp. (ECS), 2003, pp. 225-230.
6. M. K. Md. Arshad et al. , "UTBB SOI MOSFETs analog figures of merit: effects of GP and asymmetric DG regime", EuroSOI 2012, pp. 111-112.
7. A. Ohata, et al. , "Correct biasing rules for virtual DG mode operation in SOI MOSFETs", IEEE, Trans. on El. Dev. , vol. 52, 2005, pp. 124-125.
8. V. Kilchytska et al. , "Influence of device engineering on analog and RF performances of SOI MOSFETs," IEEE Trans. El. Dev. , vol. 50, 2003, pp. 577-588.