V t balancing and device sizing towards high yield of sub-threshold static logic gates

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2007, Pages 355-358

  Pu, Yu ^a,b,c   De Gyvez, José Pineda ^a,b   Corporaal, Henk ^a   Ha, Yajun ^c  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

^c NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

Sub threshold; Variability

Indexed keywords

DIGITAL GATE DESIGN; RING OSCILLATORS;

COMPUTER SIMULATION; DIGITAL CIRCUITS; ENERGY CONSERVATION; THRESHOLD VOLTAGE;

LOGIC GATES;

EID: 36949007563     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1283780.1283857     Document Type: Conference Paper

References (12)

1. Benton H.Calhoun, et al., "Modeling and Sizing for Minimum Energy Operation in Subthreshold Circuits," JSSC, Vol.40, No.9, September 2005
2. Alice Wang, et al., "Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits," IEEE Computer Society Annual Symposium on VLSI, April 2002
3. Benton H. Calhoun, Anantha P. Chandrakasan, "Characterizing and Modeling Minimum Energy Operation for Subthreshold Circuits," ISLPED, August 2004.
4. Benton H. Calhoun, et al., "Device Sizing for Minimum Energy Operation in Subthreshold Circuits," CICC, October 2004.
5. Alice Wang, and Anantha Chandrakasan, "A 1.80-mV Subthreshold FFT Processor Using a Minimum Energy Design Methodology" JSSC, Vol.40, No.1, January 2005
6. Bo Zhai, et al., "Analysis and Mitigation of Variability in Sub-threshold Design," ISLPED, August 2005.
7. John Keane, et al., "Subthreshold Logical Effort: A Systematic Framework for Optimal Subthreshold Device Sizing," DAC'06, July 2006
8. Joyce Kwong, Anantha P. Chandrakasan, "Variation-Driven Device Sizing for Minimum Energy Sub-threshold Circuits," ISLPED, October 2006
9. Goichi Ono, and Masayuki Miyazaki, "Threshold-Voltage Balance for Minimum Supply Operation" JSSC, Vol.38, No.5, May 2003
10. A.Bryant, et al., "Low-Power CMOS at Vdd=4KT/q," Device Research Conference, 2001
11. José Pineda de Gyvez, and Hans P.Tuinhout, "Threshold Voltage Mismatch and Intra-Die Leakage Current in Digital CMOS Circuits," JSSC, vol.39, No.1, pp. 157-168, January 2004
12. M.J.M. Pelgrom, et al., "Matching properties of MOS transistors," JSSC, vol.24, October 1989