On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations

ACM Journal on Emerging Technologies in Computing Systems

Volumn 9, Issue 2, 2013, Pages

  Chen, Yiran ^a   Wong, Weng Fai ^b   Li, Hai ^c   Koh, Cheng Kok ^d   Zhang, Yaojun ^a   Wen, Wujie ^a  

^a UNIVERSITY OF PITTSBURGH   (United States)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c POLYTECHNIC UNIVERSITY   (United States)

^d PURDUE UNIVERSITY   (United States)

Author keywords

Cache; Memories; MLC; Spintronic; STT RAM

Indexed keywords

CACHE; MLC; MULTI LEVEL CELL (MLC); PROCESS VARIATION; SPIN TRANSFER TORQUE; SPINTRONIC; STT RAMS; TECHNOLOGY NODES;

COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; DESIGN;

STATIC RANDOM ACCESS STORAGE;

EID: 84885659072     PISSN: 15504832     EISSN: 15504840     Source Type: Journal    
DOI: 10.1145/2463585.2463592     Document Type: Article

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