Processor caches built using multi-level spin-transfer torque RAM cells

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2011, Pages 73-78

  Chen, Yiran ^a   Wong, Weng Fai ^b   Li, Hai ^c   Koh, Cheng Kok ^d  

^a University of Pittsburgh   (United States)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c POLYTECHNIC UNIVERSITY   (United States)

^d PURDUE UNIVERSITY   (United States)

Author keywords

MLC; spintronic; STT RAM

Indexed keywords

CACHE DESIGN; CHIP AREAS; CRITICAL ISSUES; MLC; MULTI-LEVEL; MULTILEVEL CELL; PROCESSOR CACHE; REMAPPING; SPIN TRANSFER TORQUE; STT-RAM; TECHNOLOGY NODES;

DESIGN; LOW POWER ELECTRONICS; POWER ELECTRONICS;

STATIC RANDOM ACCESS STORAGE;

EID: 80052777077     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISLPED.2011.5993610     Document Type: Conference Paper

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