Leveraging variable function resilience for selective software reliability on unreliable hardware

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2013, Pages 1759-1764

  Rehman, Semeen ^a   Shafique, Muhammad ^a   Aceituno, Pau Vilimelis ^a   Kriebel, Florian ^a   Chen, Jian Jia ^a   Henkel, Jörg ^a  

^a KARLSRUHE INSTITUTE OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; REDUNDANCY;

DESIGN CONSTRAINTS; INSTRUCTION-LEVEL; MASKING PROBABILITY; RELIABILITY OPTIMIZATION; SOFTWARE RELIABILITY OPTIMIZATIONS; TEMPORAL REDUNDANCY; UNRELIABLE HARDWARES; VARIABLE FUNCTIONS;

SOFTWARE RELIABILITY;

EID: 84885621265     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.7873/date.2013.354     Document Type: Conference Paper

References (30)

1. R. Baumann, "Radiation-induced soft errors in advanced semiconductor technologies," IEEE TDMR, Vol. 5, no. 3, pp. 305-316, 2005.
2. S. Borkar et al., "Design and Reliability Challenges in Nanometer Technologies", IEEE DAC, pp. 75-75, 2004.
3. P. Shivakumar, M. Kistler, "Modeling the effect of technology trends on the soft error rate of combinational logic". IEEE DSN, 2002.
4. S. S. Mukherjee, C. Weaver, J. Emer, S.K. Reinhardt, T. Austin, "A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor", MICRO, pp. 29-40, 2003
5. R. Vadlamani et al., "Multicore soft error rate stabilization using adaptive dual modular redundancy", IEEE DATE, pp. 27-32, 2010.
6. D. Ernst et al., "Razor: circuit-level correction of timing errors for low-power operation," IEEE MICRO, Vol. 24, no. 3, pp. 10-20, 2004.
7. G. A. Reis, J. Chang, D. I. August, "Automatic instruction-level software only recovery", IEEE MICRO, pp. 36-47, 2007.
8. N. Oh et al., "Error detection by duplicated instructions in super-scalar processors", IEEE Transaction on Reliability, 51-1, pp. 63-75, 2002.
9. J. Hu et al., "In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability," DSN, pp. 281-290, 2006.
10. J. S. Hu et al., "Compiler-Directed Instruction Duplication for Soft Error Detection," DATE, Vol. 2, pp. 1056-1057, 2005
11. G. V. Varatkar, N. R. Shanbhag, "Energy-efficient motion estimation using error-tolerance", IEEE ISLPED, pp. 113-118, 2006.
12. V. Chippa, A. Raghunathan, K. Roy, S. Chakradhar, "Dynamic Effort Scaling: Managing the Quality-Efficiency Tradeoff", DAC, 2011.
13. M. Shafique et al., "Power-Efficient Error-Resiliency for H.264/AVC Context-Adaptive Variable Length Coding", DATE, pp. 697-702, 2012.
14. M. A. Makhzan, A. Khajeh, A. Eltawil, F. J. Kurdahi, "A low power JPEG2000 encoder with iterative and fault tolerant error concealment", IEEE TVLSI, Vol. 17, no. 6, pp. 827-837, 2009.
15. A. Heinig, M. Engel, F. Schmoll, P. Marwedel, "Improving transient memory fault resilience of an H.264 decoder", ESTIMedia, 2010.
16. Flux calculator: www.seutest.com/cgi-bin/FluxCalculator.cgi.
17. H.264 Codec JM 13.2: http://iphome.hhi.de/suehring/tml/index.htm.
18. S. Rehman et al., "Reliable software for unreliable hardware: Embedded code generation aiming at reliability", Codess+ISSS, pp. 237-246, 2011.
19. P. Giacinto et al., "An experimental Study of Soft Error in Microproces-sors", MICRO, pp. 30-39, 2005.
20. S. Z. Shazli, M. B. Tahoori, "Obtaining Microprocessor Vulnerability Factor Using Formal Methods", DFTVS, 2008.
21. M. Xie, K.-L. Poh, Y.-S. Dai, "Computing Systems Reliability: Models and Analysis", Springer, ISBN 978-0-306-48496-4, 2004.
22. IBM® XIV®: http://publib.boulder.ibm.com/infocenter/ibmxiv/r2/ index.jsp.
23. AMD PhenomTM II Processor Product Data Sheet 2010.
24. J. Gaisler, "A portable and fault-tolerant microprocessor based on the SPARC v8 architecture", DSN, pp. 409-415, 2002.
25. A. Rajendiran et al. "Reliable computing with ultra-reduced instruction set coprocessors", IEEE DAC, pp. 697-702, 2012.
26. S. Rehman, M. Shafique, J. Henkel, "Instruction Scheduling for Reliability-Aware Compilation", IEEE DAC, pp. 1288-1296, 2012.
27. S. Rehman et al., "RAISE: Reliability Aware Instruction SchEduling for Unreliable Hardware", IEEE ASP-DAC, pp. 671-676, 2012.
28. J. Cong, K. Gururaj, "Assuring Application-Level Correctness Against Soft Errors", ICCAD, pp. 150-157, 2011.
29. A. Sundaram et al., "Efficient fault tolerance in multi-media applications through selective instruction replication", WREFT, pp. 339-346, 2008.
30. E. Borin et al., "Software-Based Transparent and Comprehensive Control-Flow Error Detection", CGO, pp. 333-345, 2006.