Reliable computing with ultra-reduced instruction set co-processors

Proceedings - Design Automation Conference

Volumn , Issue , 2012, Pages 697-702

  Rajendiran, Aravindkumar ^a   Ananthanarayanan, Sundaram ^a   Patel, Hiren D ^a   Tripunitara, Mahesh V ^a   Garg, Siddharth ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

microprocessor reliability; Turing complete ISA

Indexed keywords

AREA OVERHEAD; CO-PROCESSORS; DESIGN DEFECTS; HARDWARE PROTOTYPE; HUMAN ERRORS; INSTRUCTION SET; INSTRUCTIONAL PURPOSE; LLVM COMPILERS; TECHNOLOGY SCALING; TURING-COMPLETE ISA;

FAULT TOLERANCE; SEMANTICS;

COMPUTER AIDED DESIGN;

EID: 84863543327     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2228360.2228485     Document Type: Conference Paper

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