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Volumn , Issue , 2001, Pages 150-155

Testing TAPed cores and wrapped cores with the same test access mechanism

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDARY SCAN TEST; RECONFIGURABLE; SYSTEM ON A CHIP; TEST ACCESS MECHANISM;

EID: 0001940334     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2001.915016     Document Type: Conference Paper
Times cited : (13)

References (11)
  • 2
    • 84893636657 scopus 로고    scopus 로고
    • Casbus: A scalable and reconfigurable test acces mechanism for systems on a chip
    • Paris, France, March
    • M. Benabdenbi, W. Maroufi, and M. Marzouki. Casbus: A scalable and reconfigurable test acces mechanism for systems on a chip. In IEEE Design Automation and Test in Europe (DATE), pages 141-145, Paris, France, March 2000.
    • (2000) IEEE Design Automation and Test in Europe (DATE) , pp. 141-145
    • Benabdenbi, M.1    Maroufi, W.2    Marzouki, M.3
  • 4
    • 84893652618 scopus 로고    scopus 로고
    • A structured and scalable mechanism for test access to embedded reusable cores
    • Washington, DC, October
    • E. J. Marinissen and et al. A structured and scalable mechanism for test access to embedded reusable cores. In International Test Conference, Washington, DC, October 1998.
    • (1998) International Test Conference
    • Marinissen, E.J.1
  • 5
    • 0033346855 scopus 로고    scopus 로고
    • Addressable test ports an approach to testing embedded cores
    • Atlantic City, N-J, September
    • L. Whetsel. Addressable test ports an approach to testing embedded cores. In IEEE International Test Conference (ITC), pages 1055-1064, Atlantic City, N-J, September 1999.
    • (1999) IEEE International Test Conference (ITC) , pp. 1055-1064
    • Whetsel, L.1
  • 6
    • 0032308284 scopus 로고    scopus 로고
    • A structured test re-use methodology for core-based system chips
    • Washington, DC, October
    • P. Varma and S. Bhatia. A structured test re-use methodology for core-based system chips. In International Test Conference, Washington, DC, October 1998.
    • (1998) International Test Conference
    • Varma, P.1    Bhatia, S.2
  • 7
    • 0032310132 scopus 로고    scopus 로고
    • Hierarchical test acces architecture for embedded cores in an integrated circuit
    • Dana Point, CA, April
    • D. Bhattacharya. Hierarchical test acces architecture for embedded cores in an integrated circuit. In IEEE VLSI Test Symposium (VTS), pages 8-14, Dana Point, CA, April 1998.
    • (1998) IEEE VLSI Test Symposium (VTS) , pp. 8-14
    • Bhattacharya, D.1
  • 8
    • 0003880595 scopus 로고    scopus 로고
    • A novel approach for designing a hierarchical test access controller for embedded core designs in an soc environment
    • Montreal, Quebec, Canada, May
    • B. Dervisoglu and J. Swamy. A novel approach for designing a hierarchical test access controller for embedded core designs in an soc environment. In 4th IEEE International Workshop on Testing Embedded Core-Based System-Chips, pages 1.4.1-1.4.7, Montreal, Quebec, Canada, May 2000.
    • (2000) 4th IEEE International Workshop on Testing Embedded Core-based System-chips , pp. 141-147
    • Dervisoglu, B.1    Swamy, J.2
  • 9
    • 0031361926 scopus 로고    scopus 로고
    • An ieee 1149.1 based test acces architecture for ics with embedded cores
    • Washington, DC, November
    • L. Whetsel. An ieee 1149.1 based test acces architecture for ics with embedded cores. In IEEE International Test Conference (ITC), pages 69-78, Washington, DC, November 1997.
    • (1997) IEEE International Test Conference (ITC) , pp. 69-78
    • Whetsel, L.1
  • 10
    • 84893681522 scopus 로고    scopus 로고
    • A new compression/decompression method for non correlated test patterns: Application to test pins expansion
    • Cascais, Portugal, May
    • W. Maroufi. A new compression/decompression method for non correlated test patterns: Application to test pins expansion. In IEEE European Test Workshop (ETW), Cascais, Portugal, May 2000.
    • (2000) IEEE European Test Workshop (ETW)
    • Maroufi, W.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.